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Altera_Forum
Honored Contributor I
739 Views

Simple question about SDI IP

Hi to all, 

I have a very simple and basic question about the SDI IP. 

I'm using a Cyclone V GX. 

I'm trying to acquire a SDI SMTPE-292M signal (HD-SDI). 

Do I needs have to use the reconfigurator block for the transceiver? Or I couldn't implement it? 

In my opinion I don't need it, first because it's only a try, and also because the signal is HD-SDI for sure, I think I won't need to reconfigure dynamically the transceiver. 

If it's possible not to use the reconfigurator, how will I have to connect the "sdi_reconfig_togxb" and "sdi_reconfig_fromgxb signals"? (Above all the first, since it's an input). 

 

Thank you
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7 Replies
Altera_Forum
Honored Contributor I
30 Views

Were you able to figure out a solution? I cannot get HD-SDI working still.

Altera_Forum
Honored Contributor I
30 Views

Hello mbp2014, 

finally I was able to acquire SDI signal, but I used the SDI II IP. No way the SDI IP worked for me. 

With Quartus 13.1 and SDI II IP all worked for me. 

Anyway, I used a reconfigurator: the Transceiver Reconfiguration Controller (alt_xcvr_reconfig). The only setting I decided is Number of reconfiguration interfaces = 1. I tied the "reconfig_to_xcvr" and "reconfig_from_xcvr" with the corrispondent signal in the SDI II IP. The other signals are all untied (not used, in fact I don't want to control dinamically the reconfigurator). 

The IP works well and gives useful informations as line number, format of the video in ecc. It's capable to output 20 bit format video, so I had to cut 2 bits for plane because I had a 16 bit interface. But all went well. 

 

I hope the same for you. 

 

Bye
Altera_Forum
Honored Contributor I
30 Views

Thanks for replying, faust861. It's good to hear that it worked for you. I'm attempting to use SDI II now as well. By the way, when you reduced to 16bit, did you connect Altera's Clocked Video Input to the SDI II receiver? I'm curious if the CVI can decipher the SDI data when truncated to 16bits 

 

Thanks again!
Altera_Forum
Honored Contributor I
30 Views

You are welcome mbp2014 :) 

Sorry but I can't answer your second question, because I directly use the 16bit stream sending it to the VIP of a Texas Processor (Da Vinci). 

Anyway, its behaviour was very good, treating this stream as a standard, so I'm quite confident that even CVI can treat that stream well. 

I don't remember very good, but I think I saw the data stream coming out from SDI II IP on Signal Tap, and the first two bit (MSB) were always tied to 0, so I think that truncating them is not a problem.  

 

Anyway please let me know, because the issue is interesting :) 

Bye
Altera_Forum
Honored Contributor I
30 Views

faust861, can you confirm which bits you truncated for your design from the SDI's [19:0] rx_dataout bus? 

 

I was thinking of using bit [19:12] & [9:2] to connect to the CVI block. Is this correct?
Altera_Forum
Honored Contributor I
30 Views

Yes, I did exactly the same!

Altera_Forum
Honored Contributor I
30 Views

I tried the [19:12] & [9:2] bits from the SDI rx core to the CVI block and it worked. Thanks for the help :)

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