I have implemented a PCIe Gen2 x4 interface in a Cyclone V (simulation only - I don't own the appropriate dev kit yet!)
The example simulation using the host-side BFM modules works fine, but I wish to take this further and inject some custom user data into the host side module which can be sent over to the FPGA via the PCIe interface. Is this something that I can do with the Intel generated components? If so, how would I do this?
Otherwise, am I going to need a different set of verification IP? If so, are there any verification IPs that I can pick up for free?
(This is all hobbyist stuff so I don't have budget to spend!)
Thanks for reaching, not sure how you gonna perform as different applications might link to different kinds of solutions.
However, I do lay down some of the suggestions for performing read and write between PCIe and FPGA.
You may look at PCIe IP example at the below link.
Let me know if this is helpful.
We do not receive any response from you to the previous question that I have provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you
I have been looking at the example you linked to (for Cyclone V devices).
Unfortunately I don't have a development kit that I can use this with at the moment. I am having troubles getting hold of one. I don't know if this is something you might be able to help with?
I do not understand your question on "having trouble getting hold of one". Can you clarify more on it?
Anyway, you can try to run the design example simulation inside Quartus. You can generate a testbench based on the provided design example and run the simulation using Modelsim for Cyclone V PCIe Hard IP by referring to user guide Chapter 2 above. https://www.intel.com/content/www/us/en/docs/programmable/683524/18-0/datasheet.html
Yes I can clarify. I don't have a cyclone V GT development kit with a PCIe interface. Any that I have found are very expensive and I can't afford them. Please bare in mind I am doing all this as a hobby NOT as a business.
I will see if I can get your simulation to work later. Simulation will be useful for now as long as I can simulate some custom traffic. I have already run the Intel example simulations for the pcie gen2 interface as detailed in the user guide.
I wish to follow up with you on this case. Do you still have further inquiries on this issue? I will remain this loop open for 3 days.
If we do not receive any response from you to the previous answer that I have provided.
This thread will be transitioned to community support.
If you have a new question, feel free to open a new thread to get support from Intel experts.
Otherwise, the community users will continue to help you on this thread. Thank you