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Simulating RS232 UART IP Core in VHDL

FHint
New Contributor II
2,233 Views

Hello,

I am currently working on a FPGA design containing a UART interface and have choosen the Intel RS232 UART IP Core from the University Program to use for this.

I would like to simulate the IP Core with ModelSim first and have therefore created a Qsys testbench that consists of a clock source BFM, reset source BFM, Avalon-MM master BFM, conduit BFM, custom component (that drives the IP core's ports) and the IP core itself.

The IP core is configured the following way:

Interface: Streaming
Baud: 9600
Data: 8 Bits
Start: 1 Bit
Parity: None

The system can be generated without any errors but produces the following warning:

Warning: rs232_0: No files generated for fileset SIM_VHDL

When trying to simulate the testbench in ModelSim it says:

# ** Error: <simulation_folder>/<testbench_name>.vhd(11): (vcom-1598) Library "<testbench_name>_altera_up_avalon_rs232_171" not found.

Is the problem, that I'm trying to simulate the Qsys testbench in VHDL?
The custom component is written in VHDL so I'm not able to simulate it in Verilog.

I am using Quartus Standard 19.1.

Best Regards,
Florian

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19 Replies
ShengN_Intel
Employee
2,123 Views

Hi,

 

Seems like modelsim can't find that module.

You have to manually add the .qip and .sip files after generating the IP core. 

The .qip will be located in <generation_directory>/synthesis/.qip 

The .sip will be located in <generation_directory>/simulation/.sip 

 

You can also try on Modelsim Simulation Setup Script (msim_setup.tcl) in testbench/Mentor. Refer to manual here or video here.

**Note: This feature is available in the Intel Quartus Prime Pro Edition software for all devices.
              This feature is available in the Intel Quartus Prime Standard Edition software for only Intel Arria 10 devices.

 

Best regards,

Sheng

p/s: If any answer from community or Intel support are helpful, please feel free to mark as solution and give Kudos.

 

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FHint
New Contributor II
2,116 Views

Hi Sheng,

thank you for the quick answer!

How do I generate the RS232 UART IP Core solely? I have added the component in Platform Designer, but I can only generate the whole subsystem including the IP Core and not the IP Core only. Therefore the synthesis and simulation folders for the IP Core are not generated.

Regarding the IP Core only this folder is created:

<subsystem_name>\altera_up_avalon_rs232_171\synth

which contains some Verilog and VHDL files. When generating the subsystem the "Simulation" box was ticked and all language options were set to "VHDL".

Is there a way to generate the RS232 UART IP Core solely?

Best regards,
Florian

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ShengN_Intel
Employee
2,112 Views

Hi Florian,

You are using standard version right? This <subsystem_name>\altera_up_avalon_rs232_171\synth file format you mention can only be created by pro version but not standard version. If for standard version usually there will be synthesis, simulation or testbench files generated based on your choice. Below attached an uart RS232 ip core project file created using Quartus 19.1 Standard for your reference.

 

Thanks,

Best Regards,

Sheng

 

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ShengN_Intel
Employee
2,106 Views

Hi Florian,

 

Sorry for confusion. I think you might be using other device family. You may have to include the .qsys file to include all the submodules.

 

(If still cannot you have to use Modelsim Simulation Setup Script msim_setup.tcl in sim/Mentor. Refer to manual here or video here.)

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ShengN_Intel
Employee
2,069 Views

Hi Florian,

 

I further found out that testbench system for UART RS232 ip core can only be simulated under verilog language but not VHDL. Seems like the verilog modules can't be picked up by VHDL file if VHDL is used. Below attached a sample project for your reference.

 

Thanks,

Best regards,

Sheng

p/s: If any answer from community or Intel support are helpful, please feel free to mark as solution and give Kudos.

 

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FHint
New Contributor II
2,038 Views

Hi Sheng,

I have tried to take a look at the unsaved_tb.qsys system you had attached, but the platform designer cannot find the component, as you can see in the following image.

FHint_0-1649149336093.png

I am using the Quartus Standard 19.1 edition - is that a problem?

Best Regards,
Florian

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ShengN_Intel
Employee
2,029 Views

Hi Florian,

 

I think there are some files missing there. Below attach another file for your reference. Try to remove unsaved.qsys and include only unsaved_tb.qsys which is .qsys file of testbench system generated. Then do compilation and RTL simulation. You can add more signals by right-clicking in modelsim object panel or use command add wave -r /*

 

Best regards,
Sheng
p/s: If any answer from community or Intel support are helpful, please feel free to mark as solution and give Kudos.

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ShengN_Intel
Employee
1,985 Views

Hi Florian,


Any further update or consideration? Or should I consider that case to be closed?


Best regards,

Sheng

p/s: If any answer from community or Intel support are helpful, please feel free to mark as solution and give Kudos.


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FHint
New Contributor II
1,977 Views

Hi Sheng,

when opening the unsaved_tb.qsys the same error as mentioned above appears again. The component "unsaved 1.0" wasn't found or could not be instantiated.

I am not really sure what I should expect if the unsaved_tb.qsys worked - my problem will still be that I can not run my VHDL simulation without the VHDL model of the RS232 IP core. This won't change with the files you sent me, does it?

As long as there is no way to include the RS232 IP core in a qsys testbench generated as VHDL I cannot continue with it.

Best Regards,
Florian

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ShengN_Intel
Employee
1,959 Views

Hi Florian,

 

I try with other IPs generated in VHDL can be simulated properly but UART RS232 IP (VHDL) cannot. I found this previous KDB https://www.intel.com/content/www/us/en/support/programmable/articles/000080465.html at which RS232 UART IP generated in VHDL can't be simulated properly because of simulation files missing. Workaround is select Verilog while generating the RS232 UART IP. Feedbacks from design team for this previous KDB are:

  • To update issue exist in 19.1 Std and well, I am creating a KDB to educate customer with workaround
  • This is a legacy IP that is not being actively maintained

(Sorry for any inconvenience)

 

Below attached a zip UART RS232 IP design file under Verilog language for your reference. Tested with no component "unsaved 1.0" wasn't found error.

 

Thanks,

Best Regards,

Sheng

 

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ShengN_Intel
Employee
1,942 Views

Hi Florian,


I try with other device families. Simulation of UART RS232 IP generated in VHDL works fine in those device families. I think this legacy ip not being actively maintained for newly device family.


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FHint
New Contributor II
1,918 Views

Hi Sheng,

thank you for the information and the effort you've put into it!
How can I change the family and device of a Qsys system in the Platform Designer?
I can only find these when opening the .qsys file with a text editor and not when opening it with the Platform Designer.
Except for the instanced VHDL component mentioned above the testbench is not connected to a project.

Best Regards,
Florian

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FHint
New Contributor II
1,917 Views

Also: is there another UART component that is still maintained actively and could be used as an alternative?

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ShengN_Intel
Employee
1,899 Views

Hi Florian,


You can change device family in Quartus main window and create new qsys project. Or go to View/Device Family in platform designer to change it.


May be you can replace RS232 UART with UART {RS-232 Serial Port) Intel FPGA IP as alternative. Both are similar.


Thanks,

Best Regards,

Sheng

p/s: If any answer from community or Intel support are helpful, please feel free to mark as solution and give Kudos.


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FHint
New Contributor II
1,886 Views

Hi Sheng,

I have installed and tried to use Arria V but it still says that for rs232 no files were generated for fileset SIM_VHDL.
Which device family did you use?

I have tried using the UART you mentioned above, but unfortunately it doesn't support the stream mode that the "old" UART has. It only supports the memory mapped mode.

Best Regards,
Florian

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ShengN_Intel
Employee
1,865 Views

Florian,

 

Arria V both nativelink and setup script methods (do file .../testbench/mentor/test.do) can be simulated for RS232 UART using VHDL. Check the sample file attached below. I further try out with Arria II, Cyclone V and Stratix V all can work properly.

 

Ya. UART {RS-232 Serial Port) Intel FPGA IP only supports memory mapped. IRDA UART under university program got the same problem with VHDL language on Arria 10 as well.

 

Thanks,

Best Regards,

Sheng

 

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FHint
New Contributor II
1,852 Views

Hi Sheng,

I don't understand how you were able to simulate the attached files. When I run the mentor/test.do script with modelsim following warning message appears:

FHint_0-1650621920563.png

# ** Warning: (vsim-3473) Component instance "rs232_0 : unsaved_rs232_0" is not bound.
#    Time: 0 ps  Iteration: 0  Instance: /unsaved_tb/unsaved_inst File: <path>/test/unsaved/testbench/unsaved.vhd

Also there is no file regarding the rs232 in the unsaved_tb/simulation/submodules folder:

FHint_1-1650624769311.png

This seems to be the same behaviour that I have seen on my computer when trying to simulate with the device set to Arria V.

Best Regards
Florian

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ShengN_Intel
Employee
1,841 Views

Hi Florian,


All other device family using VHDL can simulate without error but with this Warning: (vsim-3473). Sorry for missing that warning before. I think still come back to this KDB https://www.intel.com/content/www/us/en/support/programmable/articles/000080465.html where RS232 UART only supported by verilog language for simulation. Verilog language works fine on all device families.


Thanks.


Best Regards

Sheng


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FHint
New Contributor II
1,819 Views

Hi Sheng,

ok, so it doesn't make sense for me to install and test any other additional family when this warning is always going to appear, because without the rs232 instance bound I can't watch its behaviour.

Therefore I'll have to wait until I am able to debug the component in hardware, when it arrives.

I guess the topic can be closed then.

Best Regards,
Florian

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