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Altera_Forum
Honored Contributor I
1,762 Views

Simulating custom DDR controller with ALTMEMPHY using ModelSim-Altera Starter edition

I'm designing a custom DDR controller using one instance of the ALTMEMPHY generated with the MegaWizard Plug-in Manager. The simulation files generated using Quartus II version 11.1sp2 or 13.0sp1 are mostly Verilog, but one is VHDL. The starter edition of ModelSim does not simulate mixed Verilog/VHDL. Is there a way to generate the ALTMEMPHY simulation model with Verilog files only so I can simulate my design with the ALTMEMPHY IP block?

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6 Replies
Altera_Forum
Honored Contributor I
27 Views

You should be able to already simulate your design, since it should have produced a .vo file for the VHDL that is included by the .do scripts. 

 

It gets awkward when you need to actively edit the VHDL and rerun your simulation. The best I came up with was to modify the VHDL in a separate Quartus project that compiled it to .vo, which then got included in the primary Modelsim environment. 

 

It was not a very productive arrangement, but I didn't need to work in it too much so it was OK.
Altera_Forum
Honored Contributor I
27 Views

Thanks, that got me going.  

 

I didn't realize that the .vo file was the Verilog simulation version. With the .vo file in the project and the .vhd removed, the compilations completed successfully. I had to find and include the proper libraries to start the simulation, but that was all I needed to get the simulation running.:)
Altera_Forum
Honored Contributor I
27 Views

Hello, 

 

I'm also working on this. I did success in compiling my test design (which is only an ALTMEMPHY instantiation) and start a simulation. I also did choose to "skip calibration" when I configured the ALTMEMPHY. 

I only connected the clocks, resets and set ctl_clke to '1'. 

 

I was expected to see the mem_clk alive. However, it does not happen.... 

 

What are the minimum required things to configure/check before the ALTMEMPHY is ready to work with the controller ? 

 

Franck.
Altera_Forum
Honored Contributor I
27 Views

Hi, 

 

Here are some Verilog code snips that are from my working design. It simulates in Modelsim and works on a NEEK development board (Cyclone III). 

 

DDR mphy(.pll_ref_clk(osc_clk), .global_reset_n(reset_n), 

.soft_reset_n(1'b1), 

.ctl_dqs_burst(ctl_dqs_burst), .ctl_wdata_valid(ctl_wdata_valid), 

.ctl_wdata(ctl_wdata), .ctl_dm(ctl_dm), 

.ctl_addr(ctl_addr), .ctl_ba(ctl_ba), .ctl_cas_n(ctl_cas_n), 

.ctl_cke(ctl_cke), .ctl_cs_n(ctl_cs_n), .ctl_odt(ctl_odt), 

.ctl_ras_n(ctl_ras_n), .ctl_we_n(ctl_we_n), .ctl_rst_n(reset_n), 

.ctl_mem_clk_disable(ctl_mem_clk_disable), 

.ctl_doing_rd(ctl_doing_rd), 

.ctl_cal_req(ctl_cal_req), 

.ctl_cal_byte_lane_sel_n(ctl_cal_byte_lane_sel_n), 

.ctl_clk(ctl_clk), .ctl_reset_n(ctl_reset_n), 

.ctl_wlat(ctl_wlat), .ctl_rdata(ctl_rdata), 

.ctl_rdata_valid(ctl_rdata_valid), .ctl_rlat(ctl_rlat), 

.ctl_cal_success(ctl_cal_success), .ctl_cal_fail(ctl_cal_fail), 

.ctl_cal_warning(ctl_cal_warning), 

// 

.dbg_clk(ctl_clk), .dbg_reset_n(ctl_reset_n), .dbg_addr(13'h0000), 

.dbg_wr(1'b0), .dbg_rd(1'b0), .dbg_cs(1'b0), 

.dbg_wr_data(32'h00000000), .dbg_rd_data(dbg_rd_data), 

.dbg_waitrequest(dbg_waitrequest), .reset_request_n(reset_request_n), 

// 

.mem_addr(ddr_addr), .mem_ba(ddr_ba), .mem_cas_n(ddr_cas_n), 

.mem_cke(ddr_cke), .mem_cs_n(ddr_cs_n), .mem_dm(ddr_dm), 

.mem_odt(mem_odt), .mem_ras_n(ddr_ras_n), .mem_we_n(ddr_we_n), 

.mem_reset_n(mem_reset_n), 

.mem_clk(ddr_clk), .mem_clk_n(ddr_clk_n), 

.mem_dq(ddr_dq), .mem_dqs(ddr_dqs), .mem_dqs_n(), 

// 

.aux_half_rate_clk(aux_half_rate_clk), 

.aux_full_rate_clk(aux_full_rate_clk)); 

 

The key to getting the ALTMEMPHY started is the initial state of inputs from the controller. The inputs must be in the initial state until "ctl_cal_success" is true. 

 

ctl_dqs_burst <= 2'b00; 

ctl_wdata_valid <= 2'b00; 

ctl_dm <= 4'b1111; 

ctl_addr <= 13'h0000; 

ctl_ba <= 2'b00; 

ctl_cke <= 1'b1; 

{ctl_cs_n, ctl_ras_n, ctl_cas_n, ctl_we_n} <= 4'b1111; 

ctl_mem_clk_disable <= 1'b0; 

ctl_doing_rd <= 2'b00; 

ctl_cal_req <= 1'b0; 

ctl_cal_byte_lane_sel_n <= 2'b00; 

 

I believe the important thing is to initialize inputs to their inactive states until the calibration process is complete (even when skipping calibration).  

 

It's been a while since I was working on this. So, I hope I didn't miss anything. 

 

Ken
Altera_Forum
Honored Contributor I
27 Views

Hi kpaist, 

 

Thank for your advices. I'll give it a try. 

I the mean time I figured out that the DDR controller wasn't licencied anymore. I was sure it was only available as an OpenCore Plus IP evaluation.... 

 

Best regards, 

 

Franck.
Altera_Forum
Honored Contributor I
27 Views

Hi Franck, 

 

I'm using the ALTMEMPHY, because I wanted to use my own DDR controller. I have a specific video application that shares the memory between three devices. Two are display oriented. So, an arbitrator with the appropriate priorities is part of my design. Additionally, memory bandwidth was optimized with sequential reads and writes, and bank interleaving. 

 

In any case, I got it working. I hope your project is moving ahead. 

 

Best Regards, 

Ken
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