Hi everyone!
I have created a varied alt_pll from altera MegaCore.
To test it I made a TB based on BDF such that the input signals to the alt_pll are from other block named "clk_reset_tb" which output a clock and reset as I defined inside it.
As I understood, to simulate in ModelSim-Altera using NativeLink one must to have a VHDL file format and not a BDF, so I created from the BDF a VHDL file using the file -> create/update...
I should mentioned that the VHDL file is "connecting" the blocks using the SYNTHESIZED_WIRE_0 and SYNTHESIZED_WIRE_1 internal signals.
That's Ok, However, when I tried to simulate it in ModelSim-Altera it's shows me only the internal signals - SYNTHESIZED_WIRE_0 and SYNTHESIZED_WIRE_1 as the input signals to the alt_pll block, and not the clk+reset signals I wanted.
Is there any way to present the clk and reset to ModelSim-Altera using that method (BDF)...?
ThanX in advance
