Simulation Alpha Blending Mixer IP core

[Altera_Forum]

Hi eveyone,

i want to use Modelsim to simulation Alpha Blending Mixer. I create a control block with avalon-MM interface. But it's not working. 

This is block diagram and veirilog code

alpha_blending.jpg

//-------------------------------------------------------------------

//-- Project : 

//-- Description : test pattern generator 

//-- File : generator_ip.v

//-- Rev : 1.0 

//-- Designer : Cuong.TV

//-- Date : 29 July., 2013 

//--------------------------------------------------------------------

module generator_ip

(

clock,

reset,

//-----------------------------

// dout

// Avalon ST source

dout_ready,

dout_valid,

dout_startofpacket,

dout_endofpacket,

dout_data

);

parameter WIDTH= 192;

parameter HEIGHT=1080;

parameter N = 8; // Reg with

input clock;

input reset;

input dout_ready;

output reg dout_valid;

output reg dout_startofpacket;

output reg dout_endofpacket;

output [23:0] dout_data;

//---------------signal of edge_enhance-----------------//

wire clk_en;

wire [23:0] outedge_data;

wire wrreq;

localparam [1:0] source_reset_state =2'b00,

source_control_packet =2'b01,

source_start_data_packet =2'b10,

source_data_packet =2'b11;

reg [1:0] state_sink;

reg [1:0] state_source;

reg dout_sel;

//---Frame information---//

wire [23:0] control_array_dout [0:2];

reg [1 :0] control_count_dout; //range 0 to 3

reg [23:0] control_array_din [0:2];

reg [1 :0] control_count_din;//range 0 to 3

wire [15:0] width_std;

wire [15:0] height_std;

reg [9 :0] x_count;//range 0 to WIDTH-1

reg [8 :0] y_count;//range 0 to HEIGHT-1

//---Signal for Processing Unit---//

reg [23:0] pixel_in;

reg [23:0] control_data;

wire [23:0] pixel_data;

wire enb;

wire [2 :0] edge_const;

reg busy;

//---Odd buffer---//

reg rdreq;

//---Control register---//

reg [31:0] control_reg1;

reg [31:0] control_reg2;

//-----------------------------------------------------//

assign width_std = WIDTH;

assign height_std = HEIGHT;

assign control_array_dout[0]={4'h0, width_std [7 :4], 4'h0, width_std [11: 8], 4'h0, width_std [15:12]};

assign control_array_dout[1]={4'h0, height_std[11:8], 4'h0, height_std[15:12], 4'h0, width_std [3 : 0]};

assign control_array_dout[2]={4'h0, 4'h0 , 4'h0, height_std[3 : 0], 4'h0, height_std[7 : 4]};

//------------------ generate data -------------------------//

/*

generator u1

(

.clock(clock),

.reset(reset),

.rd_request(rdreq),

//-----------------------------

// dout

// Avalon ST source

.dout_data(pixel_data)

);

*/

//-------------------Avalon source control FSM----------------// 

always @(posedge clock, posedge reset)

begin

if (reset == 1'b1)

begin

state_source <= source_reset_state;

dout_valid <= 1'b0 ;

dout_startofpacket <= 1'b0 ;

dout_endofpacket <= 1'b0 ;

control_count_dout <= 2'b0 ;

rdreq <= 1'b0 ;

control_data <= 24'b0 ;

dout_sel <= 1'b0 ;

x_count <= 0 ;

y_count <= 0 ;

end

else

begin

dout_valid <= 1'b0;

dout_startofpacket<= 1'b0;

dout_endofpacket <= 1'b0;

rdreq <= 1'b0;

dout_sel <= 1'b0;

case (state_source)

source_reset_state: begin

x_count <= 0;

y_count <= 0;

if (dout_ready == 1'b1)

begin

dout_valid <= 1'b1;

dout_startofpacket <= 1'b1;

control_data <= 24'H00000F;

state_source <= source_control_packet;

end

end

source_control_packet: begin

if (dout_ready == 1'b1)

begin

dout_valid <= 1'b1;

control_data <= control_array_dout[control_count_dout];

if (control_count_dout == 2'd2)

begin

control_count_dout <= 2'd0;

dout_endofpacket <= 1'b1;

state_source <= source_start_data_packet;

end

else

begin

state_source <=source_control_packet;

control_count_dout <= control_count_dout + 1;

end

end

end

source_start_data_packet: begin

if (dout_ready == 1'b1)

begin

control_data <= 24'H000000;//indicate DATA PACKET

dout_valid <= 1'b1;

dout_startofpacket <= 1'b1;

state_source <= source_data_packet;

rdreq <= 1'b1;

end

end

source_data_packet: begin 

dout_sel <= 1'b1;

if (dout_ready == 1'b1)

begin

dout_valid <= 1'b1;

if (x_count == (WIDTH -1))

begin

x_count <= 0;

if (y_count == (HEIGHT -1))

begin

state_source <= source_reset_state;

dout_endofpacket <= 1'b1;

end

else

begin

state_source <= source_data_packet;

y_count <= y_count + 1;

rdreq <= 1'b1;

end

end

else

begin

x_count <= x_count + 1;

rdreq <= 1'b1;

end

end

end

endcase

end

end

assign pixel_data[7:0] = 0;

assign pixel_data[15:8] = 0;

assign pixel_data[23:16] = 500;

assign dout_data = dout_sel ? pixel_data : control_data;

endmodule