- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
DDR3 UniPHY.
Can't seem to get Quick or Full calibration working in simulation. Any ideas / pointers to how to get calibration to show up in simulation? How do I know? MRS[1] never gets writing leveling bit. And with or without calibration I always see the wrong write signal timing. The reason to try: the timing of the write signals are wrong at the memory interface. DQS and DQ seem to occur about 1/3 of a cycle too soon, before DQS should based on write CAS latency of 6.Link Copied
2 Replies
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
have you looked at page 10:
http://www.altera.com/literature/hb/external-memory/emi_debug_verify.pdf- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Yep, I have.
I have gone as far as editing the _p0 and _pll0 .sv files in the Qsys-generated project, basically adding define ALTERA_ALT_MEM_IF_PHY_FAST_SIM_MODEL 0 And indeed the simulation says using regular PLL and EMIF instead of fast. But nevertheless, it seems like no actual calibration happens.![](/skins/images/7FC17B7B85029576C25F1E43CE255B51/responsive_peak/images/icon_anonymous_message.png)
Reply
Topic Options
- Subscribe to RSS Feed
- Mark Topic as New
- Mark Topic as Read
- Float this Topic for Current User
- Bookmark
- Subscribe
- Printer Friendly Page