FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
6260 Discussions

Simulation refers to wrong path of altera_mf.v and simulation hangs.


Here is the details about altera lib issue:


PLL_50_100 usage: Simulation refers to wrong path of altera_mf.v and simulation hangs.

Our design is targeted on Altera max 10. It uses PLL_50_100. We are using Questasim for simulation. Altera library files have been setup. Can see them in GUI too. Though it goes through the compilation and loading, simulation hangs with the last line being: # Time: 90 Instance: tb_ov1_top.inst_PLL_50_100.altpll_component.cycloneiii_pll.pll3

When the I break the simulation, I get below error: # Break key hit

# Break in Module MF_cycloneiii_pll at /build/swbuild/SJ/nightly/18.1std/625/l64/work/modelsim/eda/sim_lib/altera_mf.v line 16981

# Error opening C:/build/swbuild/SJ/nightly/18.1std/625/l64/work/modelsim/eda/sim_lib/altera_mf.v

# Path name 'C:/build/swbuild/SJ/nightly/18.1std/625/l64/work/modelsim/eda/sim_lib/altera_mf.v' doesn't exist.


TCL script uses below args: vsim -t 1ns -L altera_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L fiftyfivenm_ver -L work -voptargs="+acc" -classdebug +UVM_TESTNAME=ov1_top_basic_test tb_ov1_top

0 Kudos
1 Reply

hello ,

Apologize for delay in response

Did you create the top module tcl script for the simulating the design ?

How about test bench ? Is that BFM is from Intel or your own testbench ? Can you send me the design file ? I can try with try with questa and come back


Thank you ,




0 Kudos