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Altera_Forum
Honored Contributor I
898 Views

Simulink Sampling time and real-world clock parameter in clock

I am fairly new to DSP builder, can anyone explain the relationship between simulink sampling time and real world clock parameter in the clock block.  

 

Can they be set the Same? 

 

Setting simulink clock to 1Sec and clock of 1uSec will execute the hardware loop 1000 times in 1 simulation clock cycle? 

 

Can some one clarify this. 

Thanks.
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Altera_Forum
Honored Contributor I
83 Views

The Simulink Sampling Time should be set to the real world time, if you want to get rid of some delay issues. 

 

I know it only from the Xilinx blockset, but the ports describing the connection between real world and FPGA have to be set up the same way, so that simulink handles the times and delays correctly.
Altera_Forum
Honored Contributor I
83 Views

what delay issues will you get by not setting the Simulink Sampling Time to the real world time? 

 

the Simulink Clock is arbitrary, how ever you want to clock the design. logical choices are 1 which makes the elapsed Simulink time equal to the number of clock cycles that have gone by, or to the real world clock which will make it easier to see elapsed time in terms of real time 

 

you can get rounding errors when using "odd" clocks for Simulink Sampling time when running ModelSim simulation with comparison to Simulink. the tool may say the results did not match when in reality they do, there is just some rounding error between the two clocks
Altera_Forum
Honored Contributor I
83 Views

What up, in this post?

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