Sine wave generation using NCO megafunction on Max 10 FPGA development kit

[Altera_Forum]

Hi all, 

I am a Bachelor student ( new to FPGAs )trying to generate a Sine Wave using the NCO (multiplier based algorithm) megafunction on the MAX 10 fpga development kit. I have read through a lot of threads and searched online but havent found a solution for my problems. These are a few problems I have been facing.  I have set in the parameters in the NCO megafunction as per my requirements. After that I have Generated the HDL and then designed the schematic(attached).  1. The output of the NCO is a 16 bit output. So I would have to give this output to a DAC to generate the analog sinewave form. As far as i have understood this NCO output is parallel. Would I need a parallel to serial converter, if so how do I implement it? 2. After the Analysis and Synthesis, in the Pin planner how do I make the pin assignments for these 16 pin outputs ? The 16 bit DAC provided in the development kit has a serial input (DAC_DIN) is what I have gathered from the data sheet. 3. Since I was unable to figure this out, I tried to simulate the NCO in modelsim and i have been getting errors(2 of them attached others are similar). Would I have to write some verilog code for simulation (I have assumed that the Generate HDL does it all so I have only written the SDC file with create clock and derive pll clock) or for the nco algorithm? What am I missing here? 4. Is there any other way other than Modelsim to simulate and check whether my design is working.  I intend to check the generated sine wave on an oscilloscope through the DAC SMA OUT.  I would appreciate any help I can get. Thanks in advance  Regards,

[Altera_Forum]

--- Quote Start ---    I have set in the parameters in the NCO megafunction as per my requirements. After that I have Generated the HDL and then designed the schematic(attached).     --- Quote End ---    You don't need schematic, use hdl design    --- Quote Start ---   1. The output of the NCO is a 16 bit output. So I would have to give this output to a DAC to generate the analog sinewave form. As far as i have understood this NCO output is parallel. Would I need a parallel to serial converter, if so how do I implement it? 2. After the Analysis and Synthesis, in the Pin planner how do I make the pin assignments for these 16 pin outputs ? The 16 bit DAC provided in the development kit has a serial input (DAC_DIN) is what I have gathered from the data sheet.    --- Quote End ---    if DAC input is single bit then you need to serialise the 16 bits to one, DAC clock should be 16 times faster than NCO and you must provide word boundary    --- Quote Start ---   3. Since I was unable to figure this out, I tried to simulate the NCO in modelsim and i have been getting errors(2 of them attached others are similar). Would I have to write some verilog code for simulation (I have assumed that the Generate HDL does it all so I have only written the SDC file with create clock and derive pll clock) or for the nco algorithm? What am I missing here? 4. Is there any other way other than Modelsim to simulate and check whether my design is working.   --- Quote End ---    modelsim compiles hdl desings

[Altera_Forum]

Hi, 

 Thank you for the reply.  How can I use the hdl ? Please can you elaborate ? For now, I have modified the .bdf and the pin planner assignments as per your suggestion. I have used a 16Mhz clock with 50 % duty cycle as the DAC_SCLK pin A7 Further, to set the data word, I have generated a 16Mhz 90% duty cycle clock and assigned it to pin DAC_SYNC (What exactly is the pin number of this..the user guide says U1.B10? I have gone ahead and put in PIN_B10 from the drop down menu in pin Planner since U1.B10 is not available as it is). And lastly, I have assigned the out put of the parallel in serial out shift register to pin DAC_DIN pin A8. I have then programmed the board with .sof file using the BTS application. I have then got the error attached.   "Failed to read production information from this SOF in the FPGA.Please select compatible FPGA design from Configure option in the menu bar.If you still met this issue, please try to restart the BTS GUI."  Also the verilog simulation gives me errors because the NCO megafunction is not licensed. I thought that I have access to test the megafunction for some limited time even without the license. So is there any way around this?  I would be much obliged if you could kindly help me sort out this error.  Regards,