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Valued Contributor III
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Single Avalon-MM Master to Muliple Avalon-MM Slaves

I'm trying to connect multiple Avalon-MM slaves to a single Avalon-MM Master. I realize this essentially automatic using Qsys, if you're IP is defined as modules in Qsys. But all of my IP is already defined in VHDL and because of my build process, I can't (easily) create wrappers to import them into Qsys. I thought I could get Qsys to create a custom Ip (.qsys) module, but I can't figure out how to export Avalon-MM ports without attached IP. I'd happy to use a freestanding solution, if that were available. Any suggestions would be appreciated.

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Valued Contributor III
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Everything in Qsys including creating components, and connecting ports can be done in the command line if that's what you are worried about. 

 

If you want to do this outside of Qsys, you can use multiplexers to create your own switching fabric. This is going to take longer than porting your design to QSYS if you have more than a few ports to connect.
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Valued Contributor III
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It ain't pretty, but: 

 

Avalon-MM Pipeline Bridge components are relatively small. Add one for your master, with it's s0 slave port exported. Add one for every slave, with it's m0 master port exported. 

 

Alternatively, create a dummy/passthrough module which doesn't do anything other than advertise the slave port, and then exports a conduit with the Avalon signals for your VHDL to connect to. Connect that to a Pipeline Bridge with it's s0 exported, and most of the resources consumed will be by the fabric. That is a little more work, but you get rid of almost all the bridges.
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Valued Contributor III
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Thanks Ted- I'll give it a try. Altera certainly does not make this simple task very easy (which is ironic since the whole point of qsys is to make things easier).  

 

Regards
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Valued Contributor III
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I wouldn't blame Altera for this. You yourself said "I realize this essentially automatic using Qsys...". Your design choices and/or build methods in not using QSYS are making it harder for you than it needs to be.

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Valued Contributor III
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I totally blame Altera. To assume all design can be forced into a proprietary system integration tool is a marketing decision. This Altera decision intentionally makes things difficult for engineers that aren't willing to work in the way prescribed by Altera marketing. By the way, I just used the equivalent AXI version of this in the Xilinx build environment. It was easy and worked great. Score one for Xilinx.

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Valued Contributor III
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I don't get it. All FPGA vendors to my knowledge use proprietary tools. Are you really saving your organization money by avoiding them? Is it a portability question? I'm genuinely confused as to why a designer would want to avoid tools that make design quicker to do.

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Valued Contributor III
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Windows vs Linux. slick+opaque versus rough+transparent. Different ways of solving the same problem. I use both, depending on the problem.

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Valued Contributor III
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--- Quote Start ---  

I totally blame Altera. To assume all design can be forced into a proprietary system integration tool is a marketing decision. This Altera decision intentionally makes things difficult for engineers that aren't willing to work in the way prescribed by Altera marketing. By the way, I just used the equivalent AXI version of this in the Xilinx build environment. It was easy and worked great. Score one for Xilinx. 

--- Quote End ---  

 

 

I fail to see that it would be easier to achieve this with Xilinx's IP Integrator than with Altera's Qsys. 

Perhaps you are more acquainted with Xilinx's tools? 

The original post is a bit vague to me and it would help to see an actual specimen of one of your VHDL modules you want to integrate.
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Valued Contributor III
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I am also curious what attribute of your VHDL and build process prevent you from managing the interconnect with Qsys, and also what mechanism Xilinx provides that makes this type of work much easier? 

 

In Qsys, it is possible for you to create a Qsys system where you have manually instantiated the interconnect blocks that Qsys normally generates for you, but this approach would be rather tedious and you'd be well off the beaten path and on your own so to speak. And while you could certainly script it, I'm guessing your time would be better spent scripting _hw.tcl files for your VHDL (automatically generated?) components and just using Qsys.
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Valued Contributor III
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In Xilinx, I can directly instantiate a "AXI crossbar" IP core in my code. This allows me to manual connect my AXI ports to the crossbar.

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Valued Contributor III
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This is a large multinational development project with many contributors. Architectural control is from a central development organization in Switzerland. To simplify integration, interfaces are defined using standards such as Avalon-MM. Trying to coordinate many different groups using a single QSYS module is not practical.

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