FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
6422 Discussions

Single rate FIR is not synthesizable.

Honored Contributor II

Hi, my name is itay. 

I have a weird problem with the DSPBA: 

When I open the demo_AD9578 it compiles and run perfectly. 

I actually copy the same filter to my own model and I also  

make sure that all of the inputs are the same format. 


input is sfix(16)_En(15), 

coefs are the same, 

there are 17 symmetrical coefs (exactly the same as the demo), 

valid is boolean, 

ch is uint8, 

FPGA is stratix IV. 


When I run my model it doesn't compile and gives me the next error: 

"Found a non-synthesizable block in the synthesizable block" 

and points to the Single_Rate_Fir. 


What can be wrong? I am a bit frustrated about it, cause i am  

working on it for several days. 


thanks ahead, 

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Honored Contributor II

If you attach your model here, it will be much easier to see what's wrong. 


From your description, everything seems fine.
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