FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.

Slow PCIe reading data

Altera_Forum
Honored Contributor II
803 Views

I have the SoC (see attachments). Recording speed up the read speed (to/from internal RAM, external DDR) up to 6 times. The project is compiled in Quartus 11.1, 12.1 and loaded in CYCLONE IV, Arria II and obtained the same result. In SignalTap I see that read cycle on the local bus (internal Avalon) ends very quickly, but response from the PCIe compiler is delayed by 2 us (>20 cycles of 100MHz; response was analyzed by the signals 'test_out'). No options in the compiler does not help. How to increase the speed of reading data on PCIe without the use of DMA ?

0 Kudos
0 Replies
Reply