Hello Community,
I've one or two questions regarding SoC Bus Performance, but first the actual Situation:
fpga: Arria II GX AGX125
ip's i use so far: Altera DDR2 HP Controller v9.0
Altera PCI Express Compiler v9.0 (HardIP) -> 1x Lane
OpenCores JPEG Encoder (
http://www.opencores.org/project,mkjpeg)
The System get it's Imagedata over PCIe, should buffer it in DDR2, encoding it into JPEG and send it back over PCIe.
I want to use Wishbone as SoC Bus and I'm willing to extend OC JPEG Enc with Wishbone (right now using OPB). For Altera IP's, as I'm understanding right, converting between Avalon-MM and Wishbone is as easy as mapping the right ports together.
Writing through PCIe Core (DMA) should reach ~215MB/s, but Memory also have to deliver Pixel Data to JPEG Enc. (in my case around 100MB/s) in parallel. From the Wishbone Spec. I read that @100MHz WB (shared Bus) reaches 400MB/s.
1.
So what are you thinking - is the Bandwidth enough for putting all Cores on one shared WB? Or should I think about something like FML with cached FML<->WB Bridge? (
http://www.milkymist.org/doc/fml.pdf)
2.
Is the missing support for pipelined Bus transfers in WB a big performance Hit? - What are your experiences, which is the fastest way of performing PCIe<->DDR2 transfers through a SoC?
