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Altera_Forum
Honored Contributor I
855 Views

State Machine Editor with DSP Builder- HDL file not generated

Hi, 

 

I'm using the Graphical State Machine Editor with DSP Builder and I noticed that after specifying my state machine and closing the state machine editor window that the inputs and outputs did not show up on my state machine block. I saw that in the Matlab command window it said, 

"Did not find the expected State Machine HDL file, BERTester.vhd". In fact there is no HDL file in my import directory, even after pressing the Generate HDL File button in the State Machine Editor. There is also no error generated. 

 

Any help would be greatly appreciated! 

 

Best Regards, 

RUSHALE
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4 Replies
Altera_Forum
Honored Contributor I
47 Views

Actually I have the same Problem. Do you know any Solution for that problem? 

 

Thx for any help!
Altera_Forum
Honored Contributor I
47 Views

By the way I just discoverd my mistake. 

 

In the State Machine Editor Window were some error Messages. First I deleted them. 

 

When I selected "Create HDL Code" then, there were 2 errors. After solving the problems and deleting the messages again I was able to create the HDL code and my inputs and outputs appeared in my DSP design.
Altera_Forum
Honored Contributor I
47 Views

Hi Klause, 

 

Thanks for your post! I've since given up on State Machine Editor, but if I try again I'll look for error messages in the State Machine Editor window.  

 

Best Regards, 

RUSHALE
Altera_Forum
Honored Contributor I
47 Views

Hi, I'm using quartus version13.0 and want to verify whether the state machine is correct with the HDL code I have written and/or vice versa . However, I can't get HDL file generated after specifying a simple state machine using a State Machine editor. Vice versa, I also can't get to view the state machine from Verilog HDL code that I have written. Appreciate if anyone can help.

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