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Store scalar variables in DSP Adv

Altera_Forum
Honored Contributor II
815 Views

I used DSP Adv block to build a module which includes tens of scalar variables. I used to different dualmem blocks to store and modify them. Is there another efficient way to store? 

 

Thanks 

Jiuxiang
0 Kudos
10 Replies
Altera_Forum
Honored Contributor II
114 Views

Are they constant? Do you need to access more than one on any clock cycle?

Altera_Forum
Honored Contributor II
114 Views

They are not constant and may be written and/or read on any clock cycle.

Altera_Forum
Honored Contributor II
114 Views

 

--- Quote Start ---  

They are not constant and may be written and/or read on any clock cycle. 

--- Quote End ---  

 

 

if you don't want to use ram then use registers. I don't know if dspbuilder provides enable on registers(delay units), if not so use a mux to enable the path i.e. pass feedback data & new data to a dual inputs mux and select between them according to your write signal, the output of mux goes to a delay unit and fedback to input of mux to keep it if your write is not active.
Altera_Forum
Honored Contributor II
114 Views

Thank your reply. I used ModelPrim in DSP Advanced Builder. There is not register unit as I know. Now I used dualmem (ram) to save these variables and access them as you said. But it is hard to compute the delay and to set multiple mux to satisfy different access. So I want to find a more efficient way to restore the variables.

Altera_Forum
Honored Contributor II
114 Views

 

--- Quote Start ---  

Thank your reply. I used ModelPrim in DSP Advanced Builder. There is not register unit as I know. Now I used dualmem (ram) to save these variables and access them as you said. But it is hard to compute the delay and to set multiple mux to satisfy different access. So I want to find a more efficient way to restore the variables. 

--- Quote End ---  

 

 

There is sample delay unit (in effect a register) but it has no enable port so I suggested using a mux to apply enable. It should work and data would be written within one clock (set sample delay to 1). It can be read anytime.
Altera_Forum
Honored Contributor II
114 Views

see attached diagram. the register would adjust to data width so you don't need single flips repeated. 

you make one instant of this as your ram cell and instantiate it for any scalar adjusting width if required.
Altera_Forum
Honored Contributor II
114 Views

Thank your suggestion. Unfortunately, there is not register unit in Advanced DSP builder. I tried to replace it with FIFO. This works but there are 3 delay from read. Anyway this is a smart solution instead of Dualmem which is ram and slower than FIFO.

Altera_Forum
Honored Contributor II
114 Views

 

--- Quote Start ---  

Thank your suggestion. Unfortunately, there is not register unit in Advanced DSP builder. I tried to replace it with FIFO. This works but there are 3 delay from read. Anyway this is a smart solution instead of Dualmem which is ram and slower than FIFO. 

--- Quote End ---  

 

 

There is certainly a register block. I use it regularly and is called sample delay(find it some where under one of libraries of ADSPBuilder.  

It infers a register or ram depending on delay. setting it to 1 infers a register.
Altera_Forum
Honored Contributor II
114 Views

A register may be a Z^-1 block.

Altera_Forum
Honored Contributor II
114 Views

 

--- Quote Start ---  

A register may be a Z^-1 block. 

--- Quote End ---  

 

 

yes it is sample delay block(in ModelPrim library) and if set to 1 then infers a register and carries symbol of z^1. 

BTW xilinx SysGen(equivalent to Altera ADSPBuilder) has delay block as above but also has separate register block. Their register block has ports for reset and enable. Altera's sample block is naked of ports apart from D&Q
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