Stratix 10 DCFIFO Reset

[DanD]

The Embedded Memory User Guide states the following about resetting an SCFIFO or DCFIFO:

"During power up, the registers in Intel Stratix 10 devices are in undefined power and
reset states. To guarantee correct functionality, reset the FIFO Intel FPGA IP core upon
completion of configuration by asserting either the sclr or aclr signal. Reset is not
required if sclr or aclr signal is not used in the FIFO Intel FPGA IP core."

I'm confused about the last sentence. What does 'not required' and 'not used' mean in this context?

I'm taking 'not used' to mean:

1. Choose not to include sclr/aclr in the IP Catalog FIFO SCFIFO or DCFIFO generator

2. Tie aclr/sclr to '0' in a manually instantiated SCFIFO or DCFIFO component

[SyafieqS]

Dan,

Did you manage to work on this?

[DanD]

Hello -

Yes I have worked on this a bit. Can you confirm that, if reset is not included by either of these methods:

1. Choose not to include sclr/aclr in the IP Catalog FIFO SCFIFO or DCFIFO generator

2. Tie aclr/sclr to '0' in a manually instantiated SCFIFO or DCFIFO component

that there's a chance the FIFO may not function properly?

[SyafieqS]

Daniel,

Checking this internally since I am not a embedded expert. Will come back to you with updates