FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
6355 Discussions

Stratix 10 - Native PHY - Hard PRBS Configuration

HBhat2
New Contributor II
890 Views

Hi,

 

We are validating Stratix 10 SoC Dev kit with our custom FMC card @ 10G & 20G speed. We are using transceiver toolkit & the hard PRBS patterns to capture the eye.

 

We got the polynomial info from the user-guide.

For debugging purpose, we want to know the seed value or initial 64-bits of PRBS7, PRBS9,PRBS15, PRBS23 & PRBS31 patterns to cross verify the received patterns at high speed oscilloscope.

 

 

With Regards,

HPB

0 Kudos
5 Replies
CheePin_C_Intel
Employee
753 Views

Hi HPB,

 

As I understand it, you have some inquiries related to the seed for the S10 hard PRBS generator. For your information, as I search through the documentation as well as internal database, I am unable to locate any specific info on this. I am currently consulting Factory to see if they have any insight.

 

By the way, generally we would directly use the PRBS pattern, connected to scope to capture the eye without the need to know the seed value. Mind share with me further on how you will be using the seed in your debugging? This would be helpful in case Factory would like to seek clarificaiton for further information on the request. 

 

Please let me know if there is any concern. Thank you.

 

Best regards,

Chee Pin

 

0 Kudos
HBhat2
New Contributor II
753 Views

Hi,

 

Thanks for your effort for consulting your factory.

Actually our debugging team has a set-up (with 33G digital oscilloscope) to validate the protocol specific eye opening and we are testing our custom FMC card with Stratix 10 SX dev kit.

The debugging set up also supports all the PRBS patterns as supported by Intel Stratix 10 Transceiver hard PRBS with same polynomial. However, debugging team observed some discrepancy and it is doubtful whether the received pattern is PRBS31 or not. Just to cross verify the received bit sequence in the oscilloscope , we want the seed value or the first 64-bit sequence.

 

With regards,

HPB

 

0 Kudos
HBhat2
New Contributor II
753 Views

Hi @cheepinc_Intel​ ,

 

Also, we observed that as soon as the transceiver channels are loaded in the Transceiver toolkit, TX lines are driven with default pattern. Also, if we click stop, then only RX side "checker" field will be pauses, but still the TX is line is continued to toggle.

 

I think the toolkit starts transmitting without user input, the START and STOP buttons related only to receiver to check the BER and other status.

 

Can you please clarify on this behavior?

 

With regards,

HPB

0 Kudos
CheePin_C_Intel
Employee
753 Views

Hi HPB,

 

Sorry for the delay. I have been out for the past week. For your information, I have consulted Factory on this but seems like we are unable to find any specific information on the seed used in the hard PRBS block. Sorry for the inconvenience.

 

As a workaround, probably you can look into using user coded soft PRBS generator which match the PRBS required by the scope. Sorry for the inconvenience.

 

Please let me know if there is any concern. Thank you.

 

Best regards,

Chee Pin

 

0 Kudos
CheePin_C_Intel
Employee
753 Views

Hi HPB,

 

Regarding the TX line toggling, I do not have detailed information on this. However, based on my experience with previous device families, by default, the TX will send out clock pattern when it is not transfering out PRBS pattern. Not sure if you are observing clock pattern as well from the S10 TX in TTK?

 

Please let me know if there is any concern. Thank you.

 

Best regards,

Chee Pin

0 Kudos
Reply