We are using Native PHY IP for Stratix 10 and we have developed all PCS components from scratch as we are unable to reuse the Intel supported PCS blocks due to Polynomial differences in Scrambling, or unsupported 128b/132b encoding etc.
Initially we studied the L-tile transceiver user guide and thought of using PCS direct mode. Also, we wanted to use bit-slip logic to align the word in the receiver path. But, PCS direct mode doesn't support bit-slip feature as compared to Enhanced PCS.
So, can we set the native PHY in Enhanced PCS mode to reuse only bit-slip feature and we will not select any other feature of Enhanced PCS?
Setting Enhanced PCS and not using any supported features like Interlaken, 64b/66b, scrambling etc is same as PCS Direct?
As I understand it, you have some inquiries related to the Enh PCS acting as PCS Direct. For your information, as I look at the Enh PCS path block diagram in the user guide, it seems like you are not able to bypass all the internal blocks. For example, the TX gearbox, RX gearbox and block synchronizer will always be there. Therefore, in term of architecture, we cannot say it will become same as PCS direct. However, since most of the blocks can be bypassed in Enh PCS, you can perform some simulation to check if after bypassing these blocks, it can work as per your target requirement.
Please let me know if there is any concern. Thank you.