Stratix 10 SX Low Latency 40G Ethernet IP

[MBarn13]

I am attempting to use the Low Latency 40G Ethernet IP in a 1SX280HN2F43I2LPAS chip using Quartus 20.4 Pro. I am unable to get the tx_lanes_stable signal to go high or establish a link through an optical transceiver.

The locked signals from both internal PLLs miss timing to the reset synchronizers by 90+ nanoseconds. The clk_ref is being supplied a 322.265625 MHz clock that is not the correct frequency at power on and is configured through the design. The clk_status and reconfig_clk are bing supplied a 160 MHz clock.

When the clk_ref is set correctly the ATX PLL is recalibrated and then once it achieves lock the csr_rst_n, tx_rst_n, and rx_rst_n resets are asserted for 255 cycles of the 160 MHz clock.

My main questions are why are those paths failing by so much and what can I do to establish a connection?

[ZiYing_Intel]

Hi MBarn13,

Thanks for submitting the issue.

Please do allow me have some time to look into the issue and I will get back to you with findings.

Best regards,

Zi Ying

[ZiYing_Intel]

Hi MBarn13,

The reasons that might cause tx_lanes_stable unable go high are as below:

1. soft_tx_rst, tx_rst_n : Resets the IP core in the TX direction. Resets the TX PCS and TX MAC. This reset leads to deassertion of the tx_lanes_stable output signal.
2.  sys_rst, csr_rst_n : Resets the IP core. Resets the TX and RX MACs, PCS and transceivers. Note: csr_rst_n resets the Control and Status registers, except the statistics counters. sys_rst does not reset any Control and Status registers. This reset leads to the deassertion of the tx_lanes_stable and rx_pcs_ready output signals.

Best regards,

Zi Ying 

[ZiYing_Intel]

Hi MBarn13,

Since I have addressed your question and no hear any feedback from you, I am now close the case. If you have any question after the case closed. Please do feel free to submit another issue.

Best regards,

Zi Ying