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Stratix III FPGA - MegaWizard generated PLL, phase offset misalignment

Honored Contributor II



My design contains a Stratix III FPGA and through the MegaWizard I've created a PLL with 10 output clocks. The input clock = 10 MHz, and all output clocks = 66 MHz. The phase offset of each clock is 45 degree apart from each other (i.e C0 = 0 degree, C1 = 45 degree, C2 = 90 degree, C3 = 125 degree, C4 = 180 degree...C7 = 315 degree, C8 = 0 degree, C9 = 45 degree). When I bring these output clocks out to a connector and hook up to an o'scope; and verify for the phase offset consistency, some of the phase offset are not quite aligned. Is there a test set up environment to properly measure/verify the phase offset? I just want to make sure it's not the board traces that caused the distortion or the PLL, itself causes the misalignment. Please advise. 




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