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Stratix IV ALTGX rx_pll_locked failure if EyeQ enabled

Honored Contributor II

Hi all, 


I've just spent a few days trying to track down a synthesis-only issue with a Stratix IV design containing ALTGX receiver-only channels. 


The design was created in 10.1sp1 and worked fine up until the point that I regenerated the ALTGX_RECONFIG IP in 11.1sp1. I regenerated the part because I'd added the reconfig_reset port to the part. After that point, the design worked fine in simulation, but the receiver CDR PLLs failed to lock on all channels in hardware tests. I created a minimal design that isolated the issue. It appears that the ALTGX_RECONFIG component with EyeQ interface enabled does not correctly communicate with more than one ALTGX transceiver block, i.e., rx_pll_locked works for the first four channels, but not for the rest. The problem appears to be resolved in 12.1sp1, however, I don't see anything "official" in the Altera Knowledge Base that acknowledges a problem was known to exist, and that it has been fixed. 


I've filed a Service Request. I'll post the response when I get it. I've attached the design files I submitted with the service request here in case anyone with a similar transceiver configuration is interested in them. The design files target the Stratix IV GX Development Kit. There's a readme.txt in the zip file with instructions on how to rebuild the design. There are SignalTap II traces (.PNG images) in the zip showing the difference between a working and non-working design. 



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