Stratix V PCIE hardcore not detected in bios with Intel chipset C600

[Altera_Forum]

Hi all, 

 I'm using the PCIE hardcore in Stratix V with Quartus 12.1sp1dp7.  It works on a Linux PC with Intel C200 chipset family, but not with another Linux PC (the same OS, Centos 6.4) with Intel C600 chipset family. I'm wandering if the Altera PCIE hardcore needs different settings for different chipset due to compatibility issue?   Thank you very much.  Simon

[Altera_Forum]

Have you tried to determine whether its a power-on reset timing issue? 

 For example, if your FPGA does not configure before the BIOS enumerates, then the board might not enumerate correctly. You can diagnose this problem by powering-up your PC, and then hitting ESC (or whatever) to enter the BIOS, and then exit the BIOS and allow your machine to "warm boot". Ideally you could monitor an LED on the Stratix V board to confirm that its configured before you reboot, and that it stays configured during this warm boot sequence. If the board is correctly detected after the warm boot, then you know what the problem is, and a work-around.  Cheers, Dave

[Altera_Forum]

Dave, thank you for your quick reply. Sorry for being late to update.* 

I don't it's a power-on timing issue in my case. The board is programmed, then do a host reboot, during this reboot period, the PCIE bus is actually still powered, but will let the BOIS re-enumerate the board.* But it works on motherboard with Intel C210 chipset but not with Intel C600 chipset. Any ideas/thoughts are much appreciated. Thank you very much.  Simon

[Altera_Forum]

Hi Simon, 

  --- Quote Start ---   I don't it's a power-on timing issue in my case. The board is programmed, then do a host reboot, during this reboot period, the PCIE bus is actually still powered, but will let the BOIS re-enumerate the board.* But it works on motherboard with Intel C210 chipset but not with Intel C600 chipset. Any ideas/thoughts are much appreciated. Thank you very much.  --- Quote End ---    Trace the power-on sequence using SignalTap II, or a PCIe logic analyzer if you have one :)  This thread has a link to some PCIe analysis I did on Stratix IV and Cyclone IV boards.  http://www.alteraforum.com/forum/showthread.php?t=35678  Have you tried Stratix V CvP? For example, you should be able to power-up your board with an absolutely minimal FPGA configuration which configures "as fast as is possible". If that works, then you will at least know the problem is related to the power-on sequence of your design.  Cheers, Dave