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Altera_Forum
Honored Contributor I
885 Views

Stratix V PCIe - Gen3 Example Design

Dear all, 

 

I generated the simulation files for stratix v PCIe HIP using Qsys. The endpoint successfully links up to gen3 but only at a single lane(lane 0). Is this the limitation of example design or do I need further reconfiguration? 

 

Kindly assist 

 

Abdul Rafay
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Altera_Forum
Honored Contributor I
51 Views

Firstly you may need look into the gen3 core configuration in that design, see if it is Gen3x1, Gen3x4, or gen3x8?

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