FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
5949 Discussions

Stratix V PCIe - Gen3 Example Design

Altera_Forum
Honored Contributor II
942 Views

Dear all, 

 

I generated the simulation files for stratix v PCIe HIP using Qsys. The endpoint successfully links up to gen3 but only at a single lane(lane 0). Is this the limitation of example design or do I need further reconfiguration? 

 

Kindly assist 

 

Abdul Rafay
0 Kudos
1 Reply
Altera_Forum
Honored Contributor II
108 Views

Firstly you may need look into the gen3 core configuration in that design, see if it is Gen3x1, Gen3x4, or gen3x8?

Reply