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Stratix V PCIe HIP not supporting Avalon MM Gen3 x8 I/F

Altera_Forum
Honored Contributor II
1,659 Views

Can anyone say why ? 

 

I have a single EP design using Avalon MM interconnect and across Cyclone IV, Arria V and Stratix V and I want to support Gen3 X1, X4 and X8 on the Stratix V card ... 

This is a problem to switch to Avalon ST interconnect for one design point .... 

 

Any ideas on how to get around this ? 

 

Thanks, Bob.
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21 Replies
Altera_Forum
Honored Contributor II
180 Views

The core doesn't support 256 bit thus it's not able to meet gen3x8 speeds. Altera is moving to use the Avalon mm with chaining Dma. Unless you upgrade to the latest Avmm dma core, your going to be stuck with what's there :) sorry

Altera_Forum
Honored Contributor II
180 Views

Thanks Trukng, I can upgrade ... how would I do that ?  

Also, there is something called the "Merged Design" that hasd PCISIG compliance support and an application for DMA , g3dma_diag.exe ... I need to add a Bar to that design with IMEM attached to test the gen3 x8 outbound poerformance . Any ideas on how I would do that ?
Altera_Forum
Honored Contributor II
180 Views

Is there any notion of mixing ST and MM Avalon in the same design ... I have the PCIe Merged design which is a ST Avalon design and it works with Inbound traffic at Gen 3 x 8 and misses the theroretical throughput by only 3%. I now need to demonstrate Outbound performance .. and need to add a BAR with IMEM behind it but that seems to be where I run into problems ... Is it even possible and how do I exit the QSYS component named DUT that works with another component named APP. ? 

 

Thanks, Bob.
Altera_Forum
Honored Contributor II
180 Views

Hi Bob 

To upgrade to Gen3x8 PCIe Avalon-MM with DMA, you need to choose another core called "V-Series Avalon-MM DMA for PCI Express" 

User Guide is at http://www.altera.com/literature/ug/ug_pcie_avmm_dma.pdf 

 

Reference Design Gen3x8 AVMM 256-bit DMA for External DDR3 - Stratix V is available at: 

http://www.alterawiki.com/wiki/reference_design:_gen3_x8_avmm_256-bit_dma_for_external_ddr3_-_strati...
Altera_Forum
Honored Contributor II
180 Views

To upgrade to Gen3x8 PCIe Avalon-MM with DMA, please choose another core called "V-Series Avalon-MM DMA for PCI Express" 

User Guide is at http://www.altera.com/literature/ug/ug_pcie_avmm_dma.pdf 

 

Reference Design Gen3x8 AVMM 256-bit DMA for External DDR3 - Stratix V may help: 

http://www.alterawiki.com/wiki/reference_design:_gen3_x8_avmm_256-bit_dma_for_external_ddr3_-_strati...
Altera_Forum
Honored Contributor II
180 Views

To upgrade to Gen3x8 PCIe Avalon-MM with DMA, please choose another core called "V-Series Avalon-MM DMA for PCI Express" 

User Guide is at http://www.altera.com/literature/ug/ug_pcie_avmm_dma.pdf 

 

Reference Design Gen3x8 AVMM 256-bit DMA for External DDR3 - Stratix V may help: 

http://www.alterawiki.com/wiki/reference_design:_gen3_x8_avmm_256-bit_dma_for_external_ddr3_-_strati...
Altera_Forum
Honored Contributor II
180 Views

To upgrade to Gen3x8 PCIe Avalon-MM with DMA, please choose another core called "V-Series Avalon-MM DMA for PCI Express" 

User Guide is at http://www.altera.com/literature/ug/ug_pcie_avmm_dma.pdf
Altera_Forum
Honored Contributor II
180 Views

Has anyone here been successful using the AVMM PCIe Gen3x8, V-Series Avalon-MM DMA for PCI Express which in practice is an "example design" to be found in Altera_pcie installation directory? And how about the DDR3 support as external memory? 

 

I have compiled it as a TOP (with success) and programmed the final sof to a Stratix V PCIe Gen3x8 based board, but I could not get the thing to work (not even "lspci" could recognize the board at start up). 

 

Anyone can help?
Altera_Forum
Honored Contributor II
180 Views

I tried the: 

 

an708 

hip_sv_gx_x8_g3_avmm_dma256 

Pcie DMA reference design using external DDR3 memory. It compiles successfully but in Qsys I am unable to choose the generation of files for SIMULATION  

 

Issue in Qsys 

 

Generate -> Generate HDL 

Simulation: 

 

simulation: None -> ok 

simulation: anything else -> Ko 

 

 

Error: pcie_sv_hip_de_hip_status_0: wrong# args: should be 

"proc_quartus_synth name" 

while executing 

"proc_quartus_synth" 

(procedure "proc_sim_vhdl" line 2) 

invoked from within 

"proc_sim_vhdl altpcie_sv_hip_ast_hip_status_bridge" 

Error: Generation stopped, 14 or more modules remaining 

Error: ip-generate failed with exit code 1: 2 Errors, 14 Warnings 

 

 

Error: add_fileset_file: No such file 

/home/papillon-fpga/altera/14.0/ip/altera/altera_pcie/altera_pcie_hip_256_avmm/mentor/altpcie_fifo.v 

while executing 

"add_fileset_file mentor/${vf} VERILOG_ENCRYPT PATH "mentor/${vf}" 

{MENTOR_SPECIFIC}" 

(procedure "proc_sim_vhdl" line 19) 

invoked from within 

"proc_sim_vhdl altpcie_256_hip_avmm_hwtcl" 

Error: Generation stopped, 7 or more modules remaining 

Error: ip-generate failed with exit code 1: 2 Errors, 12 Warnings
Altera_Forum
Honored Contributor II
180 Views

The Status Output bridge is an additional compoent in Qsys, this output brige doesn't support simulation, you may need to disable the Status Output bridge in Qsys, then you should be able to generate the simulation files.

Altera_Forum
Honored Contributor II
180 Views

If you use the Reference Design Gen3x8 AVMM 256-bit DMA for External DDR3 - Stratix V at http://www.alterawiki.com/wiki/refer...r3_-_stratix_v,  

it should works out of the box. Ensure you have reboot the PC after programmed the .sof into FPGA for the PCIe link to establish.
Altera_Forum
Honored Contributor II
180 Views
Altera_Forum
Honored Contributor II
180 Views

Thank you. That is going to work. 

 

How about the previous question.
Altera_Forum
Honored Contributor II
180 Views

I assume your previous question is below: 

"I have compiled it as a TOP (with success) and programmed the final sof to a Stratix V PCIe Gen3x8 based board, but I could not get the thing to work (not even "lspci" could recognize the board at start up)." 

 

The Gen3_x8_AVMM_256-bit_DMA_for_External_DDR3_-_Stratix_V example design had been tested, it should works out of the box.
Altera_Forum
Honored Contributor II
180 Views

For your information, there is one set of DIP switch (SW6) on Stratix V dev kit related to PCIe and that is to select the lane width. 

Ensure you have set the DIP switches to factory default settings. 

Refer to Figure 4-2 of 'Stratix V GX FPGA Development Kit User Guide' at  

https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/ug/ug_svgx_fpga_dev_kit.p...
Altera_Forum
Honored Contributor II
180 Views

 

--- Quote Start ---  

For your information, there is one set of DIP switch (SW6) on Stratix V dev kit related to PCIe and that is to select the lane width. 

Ensure you have set the DIP switches to factory default settings. 

Refer to Figure 4-2 of 'Stratix V GX FPGA Development Kit User Guide' at  

https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/ug/ug_svgx_fpga_dev_kit.p... 

--- Quote End ---  

 

 

Well, a design (encrypted) was successfully programmed in the FPGA on the board and it worked... instead I was indeed referring to an example design (PCIe AVMM DMA) I was not able to send to the same path... so I would not mess with the switches on the board... 

 

Anyway, I'll try the DDR3 example as soon as I can... the only gotcha is that everything is Quartus II 14.0v and it does not migrate easily/automatically to 15v, so you gotta stick to 14.0v or manually tweak the Qsys project...  

 

 

Thank you SKBEH for what you give here.
Altera_Forum
Honored Contributor II
180 Views

Make sure you make changes to the pins. The GX version is different from the GS version. I have tested this design in a GS chip and works fine. You might want to try the design first without the DDR3 since thats another challenge.  

-Trukng
Altera_Forum
Honored Contributor II
180 Views

The issue I have now is that the Stratix V example designs for Gen3x4 or Gen3x8 use a DMA controller and a 64 bit address on the TXS ... I have Cyclone and Arria designs that use NIOS to connect to the TXS port using the CRA translation table configured via NIOS II .  

 

I am not sure how to port the design to Stratix for Gen3x4 or Gen3x8 ... I am currently telling QSYS that the TXS port width is 20 bits and running the Generate to get the Verilog RTL. I then altering the TXS width parameter to 64 bits and concatenating the upper 44 bits to the address into the TXS slave as a hard wired NIOS address -> 64 bit PCIe address translation. 

Any other ideas on how to port the original design ?
Altera_Forum
Honored Contributor II
180 Views

Can any one say how I get the CRA tables to support dynamic A2P address translation into a Stratix V gen3x4 or gen3x8 design ... I can only think that I can look at how it is implemented in Cyclone and Arria V and then see how to convert to Stratix V .

Altera_Forum
Honored Contributor II
133 Views

So I moved to the gen3x4 design and added NIOS II and some On Chip Memory ... the card works fine so far except for the gen3_led doesn't com on ... when in a gen3 slot the configuration link status indicates a 0x43 which is gen3x4 ... but no gen3_led only the L0_led and the four link leds are on indicating x4 and alive_led flashing ... tomorrow I will confirm gen3x4 operation by adding an analyzer. Almost identical designs that are gen3x8 have the same top_hw.v design where all the LED's are decoded .. the gen3_led is decoded off  

 

assign gen3_speed = tl_cfg_tl_cfg_sts[32:31] == 2'b11;  

 

I would like to find the documentation on tl_cfg_tl_cfg_sts but other elements of it like the link width appear to work. 

 

With the simulation Generation flipping out on me .... (see the other thread) I am stuck. 

 

This vector is generated by altpcie_sv_hip_ast_hip_status_bridge ... that I can't find anything on either. I guess I will try the PCIe ug from Altera. 

 

Thanks, Bob.
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