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Stratix V: is there switching latency spec for IO pins

jkhoo
Employee
344 Views

is there switching latency spec for IO pins when switching from output to input or high Z. The pins are at bank 3B pin AG30 and AH27. What is the switch over time from one state to another?

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AminT_Intel
Employee
300 Views

Hello,

 

We do not characterized that. May I know why do you want to know that? You cannot change the PIN behavior from output to input in user mode. This only can be done at Quartus and need compile. Please provide us more details about your inquiries.

 

Thank you.

jkhoo
Employee
246 Views

Hi AminT_Intel,
assign PINMAP_3B[22] = (PWRON && ~IO_MUX[0]) ? 1'bZ : vector_out[14];

Based on the statement above, we drive vector_out[14] into PINMAP_3B[22] when PWRON = 1 and IO_MUX = 1

 

Since PINMAP_3B[22] is externally loopback to PINMAP_3B[25]

 

We then capture back the pattern in PINMAP_3B[25] using the statement below.

assign CAPTURE_GRP03[0] = PINMAP_3B[25] ;

 

We initially thought that once IO_MUX is toggle, we would see the capture pattern at the same time in PINMAP_3B[25].

But on the contrary, what we saw was roughly a 3.75nm delay from the time IO_MUX is toggle to the time we capture the pattern at PINMAP_3B[25].

below are the signal tap we capture with sampling clock of 400Mhz. The pattern we drove in is 1010010110100101.

 

Altera_support_1.PNG

AminT_Intel
Employee
226 Views

Hello,

 

Thank you for the detailed explanation. As mentioned in last post, you cannot change the PIN behavior from output to input in user mode. This only can be done at Quartus and need compile.

 

Thank you

AminT_Intel
Employee
181 Views

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