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Beginner
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Stratix V pcie refclk lock problem

Good afternoon, colleagues.

 

I have a problem, I can not capture the frequency from pcie refclk.

I do everything as described:

 

1)set_instance_assignment -name IO_STANDARD HCSL -to PCIE_REF_CLK

2) set_instance_assignment -name XCVR_REFCLK_PIN_TERMINATION DC_COUPLING_EXTERNAL_RESISTOR -to PCIE_REF_CLK

3) I checked the resistance on the board. 50 ohms pull-up to the ground

 

I'm trying to run PHY PCIE PIPE. Signal pll_lock always is low.

 

I also made an incremental counter on the positive front PCIE_REF_CLK. The counter increases to 2. That is, two tact I'm still capturing. This occurs long before pin_perst (100ml)

 

What could be the problem?

Thank you in advance

 

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3 Replies
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Valued Contributor II
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If you're having trouble getting the PLL to lock in the design I suggest taking a look at the input clock waveform. Check if the input clock is mapped to the correct pin that is connected to the REFCLK in the PLL and also capture the clock to check if the edges are okay and that there's not much jitter etc. If the input clock is very dirty, the PLL will not be able to lock onto it and generate the requested output clocks.

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Beginner
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If the input clock is very dirty,

Thank's, Abraham. If other devices (lan card, vga card) work without problems in this pcie socket, can we conclude that the clocks is normally?

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Valued Contributor II
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Hmm .. you're using the Stratix V PCIe kit. The clock I'm referring to is not the PCIe System clock thats on the system (PC), but rather on the FPGA Board. All FPGA boards have a xtal oscillator or programmable oscillator which feeds the clock into the FPGA chip. If this refclk is not connected to the correct input refclk pin for the design, the PLL will not get its input clock and will never lock on.

 

This FPGA refclk can also be dirty at times due to other factors. You need to check

 

  1. Refclk input to FPGA is routed to correct pin in the FPGA and design.
  2. This same refclk is the one thats connected as input to PLL
  3. PLL in the design is configured and generated correct.

 

 

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