We have errors accessing most reconfig registers on transceiver on the Transceiver.
We’re using Stratix10 1SGLU2F50 device, compiled with Quartus Prime Pro 21.2.
We have instantiated 1 ATX PLL and 4 Native Transceivers, Transceivers are configured for custom mode. All 5 (1 ATX PLL + 4 XCVR) have reconfig bus enabled, on Avalon Bus, with Nios2 as the master.
We are issuing master_read_8 and master_write_8 commands from system console.
For each of the Transceivers and ATX PLL, we can only read read-only registers.
For example: Read to 0x481 (a read only reg) is successful, and returns value of 0x34. (tx&rx cal not busy, PreSICE has control of config bus, and tx*rx cal busy outputs are enabled)
When we try to read a read-write registers, or any writes. The bus hangs. The Read/Write input to XCVR/ATXPLL goes high, and stuck high, while waiting for waitreq to go low. Waitreq from XCVR/ATXPLL never goes low.
For Example: Reading from 0x000 or Writing to bit0 of 0x000 to take control of config bus from PreSICE, but bus hangs, write and waitreq are both stuck high.
Attached are 2 screenshots of
- Successful read of read-only registers 0x481 (value of 0x34 returned in sysconsole, but readdatabus says 0x000)
- Bus hangs when trying to read register x0.
Also another issue is that Transceiver Toolkit crashes with java error. Could be related to the r/w problem to reconfig bus.
Can you please check have you enabled the options in the TX PLL and Native PHY IP mentioned in the below link.
Also, I am sharing a script please execute it and then try to read-write the registers.
Steps to execute that script.
Step 1: Goto system console file option.
Step2: Click on execute script and select the script. Click OK.
After that try to read-write the registers.
eg. % rd_channel $phy 0 0 0x144 1
Hope this will resolve your issue.