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6098 Discussions

Stratrix 10 native phy transceiver


Hello, I have been trying 10G phy transceiver in simplex mode. Tx simplex phy and Rx simplex phy. I am using 2 transceivers  in different banks(one acts as tx in simplex mode and other as rx in simplex mode ) . Data rate for both tx and rx phy is set as 10312.5Mhz. The Tx serial clock is connected to atx pll clock out. The clock out frequency is 5156.25MHz and reference clock frequency for atx pll is 644.53125Mhz. (atx pll ref clk, tx phy transceiver are in same bank).

on the Rx phy side, the cdr ref clk is  connected to reference clk whose frequency is 644.53125MHz. (the ref clk and rx phy transceiver are in same bank).  


Tx parallel data and rx parallel data are connected .


I am using an analyzer for sending traffic to rx phy and receiving from rx phy.  The cdr_is_lockedtodata is 1 but cdr_is_lockedtoref signal is toggling.  The received data in the analyzer has some bit errors.

I tried manually locking cdr to ref clk then the analyzer is showing received clock frequency ppm deviation >2000ppm.


I have tried with 156.25 ref clk too. Still rx cdr is unable to lock to ref clk. What could be the reason the cdr is unable to lock to reference clk ?

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2 Replies

Hi Deepthi,

The cdr_is_lockedtodata is 1 but cdr_is_lockedtoref signal is toggling. If the CDR is LOCKED, it is okay the cdr_is_lockedtoref signal is toggling. This is fine if you are using automatic lock mode.

Please refer L-Tile and H-Tile Transceiver PHY User Guide and


Hi Deepthi,

As We do not receive any response from you to the previous answer that I have provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.