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Valued Contributor III
719 Views

Synthesis Java Error in Linux

Hi all, 

 

I have succesfully installed DSP Builder 9.1 (Matlab R2008b) on my Fedora 11 system. 

 

I have created and compiled some small desings without any problem and I also compiled some design examples that are available in the tool. 

 

The problem is that when I try to compile a large design, sometimes I get the following error: 

 

Error: IP Generator Error: Exception during elaboration of ejemplo_memoria: java.lang.NullPointerException 

Error: IP Generator Error: Please forward the complete log file (including the following stack trace) with your bug report: 

Error: IP Generator Error: com.altera.etc.genericentity.ElementImpl.validate(Unknown Source) 

Error: IP Generator Error: com.altera.etc.genericentity.ModuleSystemImpl.validate(ModuleSystemImpl.java:146) 

Error: IP Generator Error: com.altera.etc.genericentity.ModuleSystemImpl.validate(ModuleSystemImpl.java:146) 

Error: IP Generator Error: com.altera.etc.genericentity.ModuleSystemImpl.validate(ModuleSystemImpl.java:146) 

Error: IP Generator Error: com.altera.entity.gen.Elaborator.elaborateInternal(Elaborator.java:238) 

Error: IP Generator Error: com.altera.entity.gen.Elaborator.elaborate(Elaborator.java:158) 

Error: IP Generator Error: com.altera.entity.gen.QuartusSynthLink.elaborate(QuartusSynthLink.java:336) 

Error: IP Generator Error: com.altera.entity.gen.QuartusSynthLink.elaborate(QuartusSynthLink.java:328) 

Error: IP Generator Error: com.altera.entity.gen.main.ElaborateCommand.runCommand(ElaborateCommand.java:19) 

Error: IP Generator Error: com.altera.entity.gen.main.JvgenQuartusMain.processCommandsInternal(JvgenQuartusMain.java:325) 

Error: IP Generator Error: com.altera.entity.gen.main.JvgenQuartusMain.processCommandStream(JvgenQuartusMain.java:232) 

Error: IP Generator Error: com.altera.entity.gen.main.JvgenQuartusMain.runApp(JvgenQuartusMain.java:184) 

Error: IP Generator Error: com.altera.entity.gen.main.JvgenQuartusMain.main(JvgenQuartusMain.java:91) 

Error: Can't elaborate top-level user hierarchy 

Error: Quartus II Analysis & Synthesis was unsuccessful. 16 errors, 0 warnings 

Error: Peak virtual memory: 184 megabytes 

Error: Processing ended: Fri Apr 9 17:22:34 2010 

Error: Elapsed time: 00:00:16 

Error: Total CPU time (on all processors): 00:00:00 

 

Error: Error during compilation: Synthesis failed 

 

 

At first, I thought that it had to do with a lack of memory in Matlab, so I increased the heap memory, but it did not work. 

 

 

Does anybody know what could the problem? 

 

 

Thanks a lot in advance, 

 

 

 

 

Pablo Colodron
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Valued Contributor III
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This is clearly a bug in DSP Builder. The stack trace doesn't give much information beyond that it's failing during validation of an entity. 

 

Could you try paring down the design to see what elements cause the failure? E.g. one way to do this is to delete half the design and see if it works. If it does then the error is likely in the second half of the design so now recreate the design with just the second half and confirm that fails. Repeat until you have design that is both small and that you're happy to post on the forum so we can see what the error might be.
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