TLP prefixes on Agilex P-Tile PCIe HIP

[TejaMB]

• Are TLP prefixes also supported in bypass mode? If yes, does the HIP perform any error checking to discard the packet if we define a custom TLP prefix?
  • Would a custom TLP prefix count as "malformed TLP"?
  • Appendix D (pg 237) in the user guide says "In TLP Bypass mode, the P-Tile ... forwards TLPs to ... except for malformed TLPs".

[RongYuan · Accepted solution]

Hi,

The rx/tx_st_tlp_prfx signals can be seen by using SignalTap. In bypass mode, the IP uses configuration registers to complete link operation. Your custom TLP prefix should be able to reach FPGA after FPGA enters user mode.

Notice PCIe has rules for TLP prefix. Even you custom a TLP, that TLP still needs to meet some criteria, for example a valid TLP type.

Regards,

Rong

[RongYuan]

for example a valid TLP prefix type.

Regards,

Rong

[RongYuan]

If no further questions, I'll close this case. Thanks.