I have configured a TSE IP as 10/100/1000Mb Ethernet MAC with 1000base-x/SGMII PCS. To enable SGMII mode and TX and RX datapaths I need to access to the PCS registers space and MAC registers space through the Avalon-MM interface. I developed an FSM to access these registers and after reset, my FSM waits for the reg_busy signal to go low, before attempting any access (read or write). The problem is that the reg_busy signal, driven by the TSE never goes down, so I can't access the registers. The tse is clocked with an external oscillator at 125MHz, which is also used to clock the SignalTap (see attached file). Where am I wrong?
Reg_busy is status output signal from TSE IP. You are right, it should go low eventually.
· Perhaps you want to review your TSE design connection and initialization process and your board clocking and reset condition again.
A good debug approach will be to compare your TSE design with below reference design to aid in debug process
· Generate TSE simulation example design from TSE IP directly. Then you can run modelsim simulation to learn more about the expected TSE IP signal behaviour
· Or you can also refer to below TSE hardware reference design as guideline
I have not hear back from you for some time.
Hopefully you are doing well with your debug progress.
For now, I am setting this case to closure. Feel free to post new forum thread if you still have enquiry in future.