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Altera_Forum
Honored Contributor I
1,530 Views

TSE + Custom PCB w/Vitesse VSC8601

Hello all, 

 

I tried to refrain from posting a question along the lines of "I can't get the TSE working...please help" lines but I am stuck. I've created a custom PCB with a cyclone III 40 (C6) and a Vitesse VSC8601 Phy. I've added the vitesse custom phy code and get to the following point: 

 

InterNiche Portable TCP/IP, v3.1  

Copyright 1996-2008 by InterNiche Technologies. All rights reserved.  

prep_tse_mac 0 

Your Ethernet MAC address is 00:07:ed:ff:00:22 

prepped 1 interface, initializing... 

[tse_mac_init] 

INFO : TSE MAC 0 found at address 0x04004000 

INFO : PHY Vitesse VSC8601 found at PHY address 0x00 of MAC Group[0] 

INFO : PHY[0.0] - Explicitly mapped to tse_mac_device[0] 

INFO : PHY[0.0] - Restart Auto-Negotiation, checking PHY link... 

INFO : PHY[0.0] - Auto-Negotiation PASSED 

INFO : PHY[0.0] - Checking link... 

INFO : PHY[0.0] - Link established 

INFO : PHY[0.0] - Speed = 100, Duplex = Full 

OK, x=1, CMD_CONFIG=0x00000000 

MAC post-initialization: CMD_CONFIG=0x04000203 

[tse_sgdma_read_init] RX descriptor chain desc (1 depth) created 

mctest init called 

IP address of et1 : 192.168.0.5 

Created "Inet main" task (prio: 2) 

Created "Clock tick" task (prio: 3) 

DHCP timed out, going back to default IP address(es) 

 

Simple socket server starting up  

[sss_task] SSS listening on port 30 

created "simple socket server" task (prio: 4) 

 

 

The issue seems to have to do with transmitting. I tried looking at the tx lines using both sigal tap and an external scope but cannot see any transitions. What I cannot figure out is if it is a code issue or a hardware issue, but because of the lack of any transitions I am leaning (err, hoping) its a software/config problem. 

 

My configuration is: 

Quartus/EDS 10.0 (Web ed) 

EP3C40F484C6 

Vitesse VSC8601 

Simple Socket Server example 

...replaced flash code with hard coded MAC 

...added custom config function for vitesse phy that sets 2ns delay 

 

 

Any suggestions would be most appreciated.
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7 Replies
Altera_Forum
Honored Contributor I
46 Views

- Have you looked at the copper side of the PHY chip to make sure there is some activity? 

- You say you're not seeing any transitions on the RGMII interface (tx pins between FPGA and PHY)? Are you sure you've got things connected properly in the FPGA because this would be strange indeed. 

 

Jake 

 

P.S. I just went through a nightmare of an experience debugging a VSC8221 PHY with the TSE MAC a few months ago. Turned out to be an issue with the PHY's onchip 1.2V regulator. but let's hope that's not the case for you.
Altera_Forum
Honored Contributor I
46 Views

Is your link in Gigabit mode? Because the driver seems to say it is 100Mbit/s. In that case the frequencies on the RGMII bus change. And I think that old versions of the TSE Mac (pre 9.0, I think) don't handle the RGMII interface with 10/100MBits/s very well.

Altera_Forum
Honored Contributor I
46 Views

Thanks for the fast responses. 

 

@ jakobjones 

 

I only have activity on the RX lines. I can see those all the way into the FPGA via signaltap and they look fine. I've triple checked all the pin and internal connections. Right now I am using the tse example that shipped with the newest eds...the only thing I changed was the size of my ddr2 memory to match...everything else matches up. I looked at my power supplies again but they look good. What trouble did you have with yours? I've seen phys have PS issues before but they generally don't link up at gige speeds with noise on the analog side. This setup links up right away with 10/100/1000 no problem. 

 

@Daixiwen 

I'm using version 10.0 of everything so I believe I'm okay regarding the older 1/100 RGMII issue. The link is 100 right now but I tried on a gige link again with no success. 

 

Thanks again.
Altera_Forum
Honored Contributor I
46 Views

If you're getting a link then your PHY is probably fine. Not seeing TX activity is odd. The first thing that comes to mind is to make sure that your SGDMA controllers are set up properly. I'd drill down into the TSE mac driver and set some breakpoints to see what's going on during a transmit. make sure the interrupt is coming back from the SGDMA controller indicated that the transmit finished successfully. 

 

You could also put signaltap on the Avalon streaming connection between the SGDMA controller and the MAC and make sure you're seeing the data transfer there. 

 

Jake
Altera_Forum
Honored Contributor I
46 Views

All, 

 

Great help and suggestions here...this forum is a tremendous resource. I finally got it to work (with a very little bit of egg on my face).  

 

Signal tap was doing its job and not routing the TX DDR signals from the mac to its internals so thats why I could not see them. I rerouted them to an external header and looked at them via an Agilent InfiniiVision scope's digital inputs to see that I indeed did have clean transitions on my digital lines. Hooked the signals back up to the PHY's I/O pins and nothing. Apparently the probing of the vias close the PHY was being impeded by solder mask and it took a very specific angle to get at the TX pins. The signals looked great there afterwards, although I did increase the drive strength to maximum current from the FPGA just for good measure. So it was clearly a timing/config problem. Reviewed the default startup config of the registers (CMODE pins on the Vitesse chip) and found register 23 (0x17) had not been configured properly...the delay wasn't set since some engineer (me) didn't properly configure the CMODE resistors. For the next person I've included my configuration and init code below for the SSS: 

 

// locate this at the top of iniche_init.c 

 

void vitesse_phy_cfg() 

int x,tmp; 

printf("Configuring vitesse VSC8601 phy\n"); 

printf("REG 0 - Mode Control\n"); 

tmp = 0x1140; 

IOWR(TSE_MAC_BASE,0x80 + 0,tmp); // Enable Full duplex... 

 

printf("REG 17 - Extended phy Control\n"); 

tmp = 0x1120; 

IOWR(TSE_MAC_BASE,0x80 + 0x17,tmp); // this is the important line here...add 2ns of delay and activate actiphy 

 

printf("VSC8601 phy Registers...\n"); 

for(x=0x80;x < 0x80+29;x++) 

tmp = IORD(TSE_MAC_BASE,x); 

printf("addr: %x, dta: %x\n",x - 0x80,tmp); 

 

 

// put this at the top of SSSInitialTask 

INT8U error_code; 

INT32U x,tmp; 

 

//Print out the regs to see if it comms with any phy's 

for(x=0;x<0x320/4;x++) 

tmp = IORD(TSE_MAC_BASE,x); 

printf("addr: 0x%X, dta: 0x%X\n",x,tmp); 

//Add profile 

alt_tse_phy_profile VSC8601 = {"vitesse VSC8601", // 

0x1C1, // vitesse OUI 

0x02, // Vender Model Number 

1, // Model Revision Number 

0x1C, // Location of Status Register 

3, // Location of Speed Status 

5, // Location of duplex Status 

0, // Location of Link Status 

&vitesse_phy_cfg // Function pointer to configure marvell PHY 

 

&#12288; 

}; 

alt_tse_phy_add_profile(&VSC8601); 

 

&#12288; 

alt_tse_system_mac sys_mac = {TSE_SYSTEM_MAC(TSE_MAC)}; 

alt_tse_system_sgdma sys_sgdma = {TSE_SYSTEM_SGDMA(SGDMA_TX, SGDMA_RX)}; 

alt_tse_system_desc_mem sys_mem = {TSE_SYSTEM_DESC_MEM(DESCRIPTOR_MEMORY)}; 

alt_tse_system_shared_fifo sys_sfifo = {TSE_SYSTEM_NO_SHARED_FIFO()}; 

alt_tse_system_phy sys_phy = {TSE_SYSTEM_PHY(0, NULL)}; 

 

alt_tse_system_add_sys(&sys_mac, &sys_sgdma, &sys_mem, &sys_sfifo, &sys_phy ); 

Altera_Forum
Honored Contributor I
46 Views

I'm glad you got it figured out. Nice work. 

 

Jake
Altera_Forum
Honored Contributor I
46 Views

 

--- Quote Start ---  

 

P.S. I just went through a nightmare of an experience debugging a VSC8221 PHY with the TSE MAC a few months ago. Turned out to be an issue with the PHY's onchip 1.2V regulator. but let's hope that's not the case for you. 

--- Quote End ---  

 

 

Dear Jake! 

 

I am writing you to ask for help with debug VSC8221. 

 

We use VSC8221+ HX5004NL with Xilinx Kintex-7. 

VSC8221 work without EEPROM, with TTL generator 25 MHz (PLLMODE left floating, OSCDIS = GND, XTAL2 left floating) and internal 1.2V regulator is used (REGEN = VDD33A). 

MDC and MDIO connect to axi_ethernet (MAC on Kintex-7, (ds759_axi_ethernet)) and we can read/write VSC8221 registers. 

JTAG we do not use (TRST = DGND). 

CMODE have next configuration: 

 

CMODE0 -> 0 -> VDD33A 

CMODE1 -> 4.02 k -> VDD33A 

CMODE2 -> 22.6 k -> VDD33A 

CMODE3 -> 0 -> VDD33A 

 

We tested far-end loopback (Register 23 (17h), bit 3), WireShark show that loopback work fine. Link-up and ping packets go back without lost. 

After power-up and low-to-high transition of the NRESET pin no link-up. 

REF_FILT pin = 1,2V 

REF_REXT pin = 1V 

Copper pair A and B = 1,65V 

CLKOUT = 125MHz, but clock has bad form. 

 

 

What may be wrong in our design? 

May be, we have to assert PLLMODE or use external 1.2V power generator? 

 

We see that auto-negotiation test pulses come from link partner, but read from Register 1 (01h), bit 5 show that auto-negotiation not complete. 

Restart auto-negotiation (Register 0 (00h), bit 9) do not help. 

We think that problem with link partner, but when we use Xilinx board ML605 with Marvell 88E1111 link-up with our link partner. 

 

May be, problem with initialization? 

Does we have to write "Required PHY Register Write Sequence" (VSC8221 Data Sheet, page 126) every time when power-up VSC8221? 

We try, but it does not help. 

 

 

--- Quote Start ---  

P.S. I just went through a nightmare of an experience debugging a VSC8221 PHY with the TSE MAC a few months ago. Turned out to be an issue with the PHY's onchip 1.2V regulator. but let's hope that's not the case for you. 

--- Quote End ---  

 

 

If you have some time, write your thoughts about our problem. 

 

 

Regards, 

Abramov Egor.