FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
5887 Discussions

TSE Fifo Transmit Rdy signal

Altera_Forum
Honored Contributor II
824 Views

Hi, 

 

I am trying to use my TSE which is configured for SGMII 10/100/1000 Mbps with 2048x32 internal fifo on Tx. In the 100 Mbps link mode I see that the Rdy signal does not get asserted often to keep up with the incoming rate. 

 

The ready signal gets asserted 3 clock cycles in every 64 clock cycle samples which corresponds to about 5.85Mbps and the data is coming in at a rate of 31.25 Mbps. My application uses large buffers other than the FIFO buffers (Large buffers - 8192 Words deep) but it is still not able to absorb the incoming data rate. I have tried decreasing the IPG (inter packet gap) on the TSE to 8 from default of 12. This was of little use.. Is there any way I can resolve this issue with the TSE? 

 

The above problem is seen in 100 Mbps mode only
0 Kudos
0 Replies
Reply