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Altera_Forum
Honored Contributor I
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TSE Fifo Transmit Rdy signal

Hi, 

 

I am trying to use my TSE which is configured for SGMII 10/100/1000 Mbps with 2048x32 internal fifo on Tx. In the 100 Mbps link mode I see that the Rdy signal does not get asserted often to keep up with the incoming rate. 

 

The ready signal gets asserted 3 clock cycles in every 64 clock cycle samples which corresponds to about 5.85Mbps and the data is coming in at a rate of 31.25 Mbps. My application uses large buffers other than the FIFO buffers (Large buffers - 8192 Words deep) but it is still not able to absorb the incoming data rate. I have tried decreasing the IPG (inter packet gap) on the TSE to 8 from default of 12. This was of little use.. Is there any way I can resolve this issue with the TSE? 

 

The above problem is seen in 100 Mbps mode only
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