FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.

TSE IEEE1588 feature

Altera_Forum
Honored Contributor I
903 Views

Hello!  

I want to receive a timestamp for an incoming message. The documentation (Intel FPGA Triple-Speed Ethernet IP Core User Guide) says "In the receive datapath, the IEEE 1588v2 feature provides a timestamp for all receive 

frames. The timestamp is aligned with the avalon_st_rx_startofpacket signal." What does it mean? Can I get the timestamp from avalon bus?
0 Kudos
0 Replies
Reply