TSE IP Core v15.0 Hold Violation Bug - Intel Community

FPGA Intellectual Property

PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP

TSE IP Core v15.0 Hold Violation Bug

925 Views

This link: https://www.intel.com/content/www/us/en/programmable/support/support-resources/knowledge-base/solutions/rd05062015_805.html

states that the v15.0 version of the core had had a bug where a small hold violation may be observed when used on a Cyclone V.

I am currently seeing this using v16.1 of the core (and Quartus) with a C8 speed grade Cyclone V.

Does anyone know if the above bug still exists in v16.1 of Quartus?

Link Copied

1 Reply

325 Views

Hi NJack1,

Kindly use the workaround suggested in this KDB.

Thanks

Copy link

Community support is provided Monday to Friday. Other contact methods are available here.

Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.

For more complete information about compiler optimizations, see our Optimization Notice.