Hi,Device Family : Cyclone 4 GX Tool : Quartus version 11.0 Board/Design : Custom Board with 4 FPGAs. FPGA 1 and FPGA2 have TSE MAC instantiated. FPGA 1 and FPGA2 Connected to ethernet ports through separate MARVELL 88E1111 PHY. Test Set up : PC1-->Ethernet-->Ethernet Port 1-->FPGA1, PC2-->Ethernet --> Ethernet Port 2--> FPGA2 FPGA1->RX ----> FPGA2-->TX FPGA2->RX ----> FPGA1-->TX Observation: TX/RX on each FPGA works fine when tested independently, with RX data from TSE MAC folded back in to TX data of the same TSE MAC. Tested by sending a PING request from PC1 and PC2 respectively. This should mean that the board is working fine on both ethernet ports. When FPGA 1 is programmed and the TX and RX paths checked through signal tap, data is seen correctly at the MAC RX path. There is no data on TX as it is connected to Pins which are input. But, we see TX READY asserted indicating all is well. Now, when FPGA 2 is programmed with the TSE MAC IP, and it comes up, we see the RX path ok on both FPGAs. But, the TX READY signals are de-asserted (low) on both FPGAs. It never gets asserted again. Both FPGAs have different MAC IDs programmed by the values in the MIF file. Tx_Almost_Full threshold has been set to 3 as recommended. TX and RX Fifos are in Store and Forward mode. Both FPGAs are being programmed through separate JTAGs from different PC with the TSE MAC IP in evaluation mode (I have not bought the IP yet). So the TSE MAC is working under the tethered mode, so we dont expect any license issues -- right? What could be the problem? WHy would the TX READY get deasserted? There has been no data pumped in - so there is no question of teh fifos being full. What are the other reasons for the TX READY getting deasserted? Why would programming AND running a second MAC on a second FPGA affect the first? Any help is appreciated .. Thanks a ton in advance Krishna
What kind of signals do you have between FPGA1 and FPGA2? Could configuring the FPGA2 trigger a reset in FPGA1 and stop the TSE MAC from transmitting correctly?