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TSE - PCS only internal loopback problem

SKon1
Novice
253 Views

Hello,

 

I'm using the TSE core in a PCS only configuration on an Arria V FPGA.

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_ethernet.pdf

Data is being sent from my logic to the IP core over the "gmii_tx_d" bus while "gmii_tx_en" is high.

After power-up -I turn on the internal loopback function of the IP using the following commands :

 

Write 0x0009 to register IF_Mode (address 0x14 - page 100 in the user guide ) :

Sets the SGMII_SPEED to 1G

Sets the SGMII_ENA to '1'.

 

Write 0xC140 to register IF_Mode ( address 0x00 - page 95 in the user guide ) :

Sets SPEED_SELECTION to 1G

Sets the SGMII_ENA to '1'.

Sets LOOPBACK to '1'.

Sets RESET to '1'. 

 

In Signal Tap I'm seeing something strange.

On the Tx side ( gmii_tx_d ) - my logic CONSISTENTLY sends an Ethernet Packet that's starting with 7 bytes of 0x55 ( this is the standard Ethernet Preamble ).

On the Rx side ( gmii_rx_d ) - roughly 50% of the time I'm receiving a 7 byte ( 0x55 ) preamble as I should. But the other 50% I'm getting only 6 bytes of 0x55 back - I.E: one 0x55 is missing.

 

Notes:

1. I have 2 Signal Tap instances. One driven by the IP's "tx_clk" to capture "gmii_tx_d" and another driven by the IP's "rx_clk" to capture "gmii_rx_d". 

2. The design doesn't have timing violations.

 

Attached is a Signal Tap waveform showcasing an error event where I received only 6 bytes of 0x55 back instead of the expected 7.

 

What causes the missing 0x55 byte some of the time ?

0 Kudos
6 Replies
SengKok_L_Intel
Moderator
219 Views

Hi,

 

I can see the same behavior in simulation, and yes this is expected behavior. This behavior won't impact the functionality of the IP. For detailed info, you may refer to the following errata.

https://www.intel.com/content/www/us/en/programmable/support/support-resources/knowledge-base/soluti...

 

Regards -SK

SKon1
Novice
219 Views

So this phenomena is an inherent flaw of the Ethernet protocol ?

SengKok_L_Intel
Moderator
219 Views

This is the known behavior as per the errata. Thanks.

 

Regards -SK

SKon1
Novice
219 Views

So this means that if the receiving logic (that's connected to the TSE IP) MUSTN'T be designed to ALWAYS accept a 7 byte 0x55 preamble ?

SengKok_L_Intel
Moderator
219 Views

Yes, you are right.

 

Regards -SK

SengKok_L_Intel
Moderator
216 Views

If further support is needed in this thread, please post a response within 15 days. After 15 days, this thread will be transitioned to community support. The community users will be able to help you with your follow-up questions. 

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