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Altera_Forum
Honored Contributor I
931 Views

TSE RGMII rxdv error

Hello, 

 

i am using altera tse ip core 10/100/1000. It works very well for link 10/100. Tx direction works as well for link 1000. Rx direction is not working properly. Signal rxdv has error flag at the start of packet (viz pictures in file).  

 

I did not find some advice how to remove this error. Does have anyone experience with this error? 

 

Thanks, 

Vasik
0 Kudos
9 Replies
Altera_Forum
Honored Contributor I
62 Views

Signals on scope: 

0- Rx Clk  

1- Rx DV 

2-5 - Rx Data
Altera_Forum
Honored Contributor I
62 Views

Dear Vasek_pilsen 

did you find the solution to this problem?  

besides that, what's the software that you used which is attached on the pdf file?
Altera_Forum
Honored Contributor I
62 Views

Hello almemar, 

 

not yet, it loos like the problem is on phy layer. 

 

Pictures are screenshots from scope. 

 

V.
Altera_Forum
Honored Contributor I
62 Views

Hello, 

 

the gigabit link issue is solved. Altera TSE MAC works correctly. The problem is in timing from Marwell 88E1111. 88E1111 has two modes for RGMII RX Clk delay. It is necessary to choose second mode. Then it works correctly. 

 

Cheers, 

Vaclav Kraus
Altera_Forum
Honored Contributor I
62 Views

Hello Vaclav,  

Thanks for the post, could you point to us from where to choose the 'second mode'. Is it in sopc or where? could you post some screenshots?  

Regards,
Altera_Forum
Honored Contributor I
62 Views

And also one more thing, I hope you may not mind.  

about the scope, could you post the name of this scope.  

regards,
Altera_Forum
Honored Contributor I
62 Views

Hello Vaclav,  

could you please contact me in person if you don't want to post your solution. I'm really in a hurry and I've to show a solution by next week to my boss.
Altera_Forum
Honored Contributor I
62 Views

Hello almemar, 

 

Rx CLK delay is a feauture of PHY chip. I use Marwell 88E1111. There is register Extended PHY Specific Control Register (offset 20). This register contains bit RGMII Receive Timing Control (bit 7). This bit selects mode of Rx Clk Delay. When you write log. 1 to this bit then additional delay is created. Then it is necessary perform sw reset of PHY chip. 

 

There is another solution (it is possible to put PLL to RX Clk then it is possible create delay in a FPGA). 

 

I use this scope: testequipmentconnection.com/39969/Tektronix_MSO4034.php 

 

Cheers, 

Vaclav
Altera_Forum
Honored Contributor I
62 Views

Thanks Vaclav for reply,  

I've tried to follow your lead, but unlucky i couldn't find exactly what you mentioned.  

except this c code which I think it should be in the NiosII part? is that correct?  

 

http://www.emdebian.org/~zumbi/mx53/u-boot-fsl/drivers/net/phy/phy.c 

Sorry for bothering you, but I have to make sure we're on the same page.  

My platform : de2-115 ( cyclone iv e )  

my template : Web server on de2-115 

Ethernet: TSE 

how could I reach to the register that you mentioned? by commands? Q II? or Nios II?  

Sincerely
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