FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP

TSE RX Problem

Honored Contributor II

Hello to all, 


I´d tried get my system work. But it seems to be an endloss story. 


Iám using the Triple Speed Ethernet IP with 10/100/1000 Ethernet MAC. with 2 SGDMA´s one RX one TX and Descriptor Memory... 

Sending Frames is no Problem. It works fine. But on Receive Side there are still some problems. I have init the MAC-CMD-Register with 


MACwrite(0x02,0x00000033); // enable TX_ENA and RX_ENA PROMIS_EN PAD_EN 


Then initialize the RX SGDMA  


// Set interrupts for the sgdma receive device --> IEGLOBAL, IE_DESCRIPTOR_COMPLETED Interrupt alt_avalon_sgdma_register_callback( devrx, &rx_ethernet_isr, 0x00000014, NULL ); // Create sgdma receive descriptor alt_avalon_sgdma_construct_stream_to_mem_desc( &descriptor3, &descriptor4, rxbuf, 0, 0 ); // Set up non-blocking transfer of sgdma receive descriptor alt_avalon_sgdma_do_async_transfer( devrx, &descriptor3 );  


If I try this the interrupt will never be executed. But when i change Interrupt-source to IE_ERROR the interrupt works. But where does this Error come from??? 


May you can help. 




0 Kudos
1 Reply
Honored Contributor II

Hi to all. 


May be it´s helpful for other users. I solved the problem by increasing the RX/TX Fifo in the TSE MAc from 512x32 to 2048x32. I don´t know why this is key. But now the System runs perfect. The aFramesReceivedOK Counter increments with every message i sent...
0 Kudos