FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
6356 Discussions

TSE SGMII with Soft-CDR and Marvel 88E1111, receive clock

Altera_Forum
Honored Contributor II
1,084 Views

Hi guys, 

 

I am at a board design right now including a Stratix IV E FPGA and the Marvel 88E1111 phy. The SGMII pins of the phy are connected to the FPGA via true LVDS buffers. The 88E1111 has a 625Mhz rx_clk which should be used if the MAC does not support clock recovery. Do I need to connect this clock if the TSE core is configured as "10/100/1000Mb Ethernet MAC with 1000BASE-X/SGMII PCS"? 

I guess no because the datasheet of the TSE mentions that Soft-CDR is supported and I cannot find a suitable receive clock input port on the TSE. 

All I have is a 125MHz dedicated clock input which I can take from the 125clk output pin of the 88E1111 (or a dedicated clock source). Am I right? 

 

I compiled the core within my test project already with success (no timing errors etc). 

 

Thanks for your help. 

 

Jan
0 Kudos
1 Reply
Altera_Forum
Honored Contributor II
326 Views

Did you finished it yet? I have same phy and also a stratix IV but it wont work. I want to connect a MII interface with the tse/sgmii core.

0 Kudos
Reply