I am currently building a design with a Micrel (now MicroChip) KSZ9031RNX PHY and a TSE MAC. The TSE is version 16.1 in a Cyclone IV FPGA.
The problem occurs on the RGMII bus, and is most likely caused by different versions of the RGMII standard supported by the PHY and the MAC. The PHY supports the 2.0 timing standard, and as far as I can see, the MAC the 1.3 standard.
Without modifications, transmission fails at all speeds and reception fails at 1G speed.
Inverting the GTX_CLK signal to the PHY relative to the MAC seems to make transmission work at all speeds, but a similar trick on the RX_CLK breaks the 100M reception and does not make the 1G work.
The PHY has the option of adjusting pad skew for all TX and RX interface pins, but my attempts with this has not been successful so far. The adjustment range is +/- 1 ns, and I think that this is not enough to solve the problem.
The solution is most likely to introduce a delay on the RX interface, but where the TX timing can be verified since I have the specifications in the PHY datasheet, I can't seem to find any specifications of what the MAC expects on the RX interface.
Does anybody know if RGMII 2.0 support is in the pipeline for the TSE?
The KSZ9021 supports RGMII 1.3, but is not recommended for new designs, so I don't want to go in that direction.
Any recommendations about how I solve this problem would be highly appreciated.
Best regards
Erik
