TSE in SGMII Mode with external FIFO and PLL for PCS Ref Clock

[Altera_Forum]

Hi everybody, 

I try to use the Altera TSE in SGMII Mode with external FIFO. My board is a SoCKit. I need a 125 MHz signal for the pcs_ref_clk and want to keep it simple and do not change the SI5338 clock generator.  If I connect the hsmc_ref_clk directly to the pcs_ref_clk from the TSE everything is compiling but for sure it is the wrong frequency because hsmc_ref_clk has a frequency of 100MHz. If I place a PLL and feed it with the hsmc_ref_clk and set the output to 125 MHz, I get some error messages at the fitter step when compiling. You can see the error messages below.  Anyone have a suggestion what can I do to get the right frequency?    Error (14996): The Fitter failed to find a legal placement for all periphery components Info (14987): The following components had the most difficulty being legally placed: Info (175029): global or regional clock driver pcs_clk:pcs_clk_inst|pcs_clk_0002:pcs_clk_inst|altera_pll:altera_pll_i|outclk_wire~CLKENA0 (49%) Info (175029): auto-promoted clock driver soc_system:u0|soc_system_eth_tse_0:eth_tse_0|altera_xcvr_custom:i_custom_phyip_0|av_xcvr_custom_nr:A5|av_xcvr_custom_native:transceiver_core|av_xcvr_native:gen.av_xcvr_native_insts.gen_bonded_group.av_xcvr_native_inst|av_pcs:inst_av_pcs|av_pcs_ch:ch.inst_av_pcs_ch|av_hssi_tx_pld_pcs_interface_rbc:inst_av_hssi_tx_pld_pcs_interface|pld8gtxclkout~CLKENA0 (36%) Info (175029): auto-promoted clock driver soc_system:u0|soc_system_eth_tse_0:eth_tse_0|altera_xcvr_custom:i_custom_phyip_0|av_xcvr_custom_nr:A5|av_xcvr_custom_native:transceiver_core|av_xcvr_native:gen.av_xcvr_native_insts.gen_bonded_group.av_xcvr_native_inst|av_pcs:inst_av_pcs|av_pcs_ch:ch.inst_av_pcs_ch|av_hssi_rx_pld_pcs_interface_rbc:inst_av_hssi_rx_pld_pcs_interface|pld8grxclkout~CLKENA0 (15%) Error (14986): After placing as many components as possible, the following errors remain: Error (175001): Could not place 1 global or regional clock driver, which is within Altera PLL pcs_clk Info (14596): Information about the failing component(s): Info (175028): The global or regional clock driver name(s): pcs_clk:pcs_clk_inst|pcs_clk_0002:pcs_clk_inst|altera_pll:altera_pll_i|outclk_wire~CLKENA0 Error (16234): No legal location could be found out of 82 considered location(s). Reasons why each location could not be used are summarized below: Error (15123): The following global or regional clock driver locations cannot route to all the required clock core fanouts Info (175027): Destination: Clock core fanout containing node soc_system:u0|soc_system_eth_tse_0:eth_tse_0|altera_eth_tse_pcs_pma_phyip:i_tse_pcs_0|altera_tse_top_1000_base_x_strx_gx:altera_tse_top_1000_base_x_strx_gx_inst|altera_tse_top_sgmii_strx_gx:U_SGMII|altera_tse_top_tx_converter:U_TXCV|altera_tse_a_fifo_24:U_DSW|altera_tse_sdpm_altsyncram:U_RAM|altsyncram:altsyncram_component|altsyncram_4vl1:auto_generated|ram_block1a0 and 9 other node(s) driven by auto-promoted clock driver soc_system:u0|soc_system_eth_tse_0:eth_tse_0|altera_xcvr_custom:i_custom_phyip_0|av_xcvr_custom_nr:A5|av_xcvr_custom_native:transceiver_core|av_xcvr_native:gen.av_xcvr_native_insts.gen_bonded_group.av_xcvr_native_inst|av_pcs:inst_av_pcs|av_pcs_ch:ch.inst_av_pcs_ch|av_hssi_tx_pld_pcs_interface_rbc:inst_av_hssi_tx_pld_pcs_interface|pld8gtxclkout~CLKENA0 and global or regional clock driver pcs_clk:pcs_clk_inst|pcs_clk_0002:pcs_clk_inst|altera_pll:altera_pll_i|outclk_wire~CLKENA0 Info (175029): 44 locations affected Info (175029): CLKCTRL_R64 Info (175029): CLKCTRL_R65 Info (175029): CLKCTRL_R66 Info (175029): CLKCTRL_R67 Info (175029): CLKCTRL_R68 Info (175029): CLKCTRL_R69 Info (175029): CLKCTRL_R40 Info (175029): CLKCTRL_R41 Info (175029): CLKCTRL_R42 Info (175029): CLKCTRL_R43 Info (175029): CLKCTRL_R44 Info (175029): CLKCTRL_R45 Info (175029): and 32 more locations not displayed Error (175006): Could not find path between source fractional PLL and the global or regional clock driver Info (175026): Source: fractional PLL pcs_clk:pcs_clk_inst|pcs_clk_0002:pcs_clk_inst|altera_pll:altera_pll_i|general.gpll~FRACTIONAL_PLL Info (175013): The fractional PLL is constrained to the region (0, 14) to (0, 63) due to related logic Info (175021): The fractional PLL was placed in location FRACTIONALPLL_X0_Y15_N0 Error (175022): The global or regional clock driver could not be placed in any location to satisfy its connectivity requirements Info (175029): 8 locations affected Info (175029): CLKCTRL_G12 Info (175029): CLKCTRL_G13 Info (175029): CLKCTRL_G14. Already placed at this location: auto-promoted clock driver soc_system:u0|soc_system_hps_0:hps_0|soc_system_hps_0_fpga_interfaces:fpga_interfaces|h2f_rst_n~CLKENA0 Info (175013): The auto-promoted clock driver is constrained to the region (42, 35) to (89, 81) due to related logic Info (175015): The HPS_INTERFACE_CLOCKS_RESETS soc_system:u0|soc_system_hps_0:hps_0|soc_system_hps_0_fpga_interfaces:fpga_interfaces|clocks_resets is constrained to the location HPSINTERFACECLOCKSRESETS_X52_Y78_N111 due to: User Location Constraints (HPSINTERFACECLOCKSRESETS_X52_Y78_N111) Info (14709): The constrained HPS_INTERFACE_CLOCKS_RESETS drives this auto-promoted clock driver Info (175029): CLKCTRL_G15. Already placed at this location: auto-promoted clock driver soc_system:u0|soc_system_eth_tse_0:eth_tse_0|altera_xcvr_custom:i_custom_phyip_0|av_xcvr_custom_nr:A5|av_xcvr_custom_native:transceiver_core|av_xcvr_native:gen.av_xcvr_native_insts.gen_bonded_group.av_xcvr_native_inst|av_pcs:inst_av_pcs|av_pcs_ch:ch.inst_av_pcs_ch|av_hssi_rx_pld_pcs_interface_rbc:inst_av_hssi_rx_pld_pcs_interface|pld8grxclkout~CLKENA0 Info (175029): CLKCTRL_G8 Info (175029): CLKCTRL_G9 Info (175029): CLKCTRL_G10 Info (175029): CLKCTRL_G11 Error (175007): Could not find uncongested path between source PLL output counter and the global or regional clock driver Info (175026): Source: PLL output counter pcs_clk:pcs_clk_inst|pcs_clk_0002:pcs_clk_inst|altera_pll:altera_pll_i|general.gpll~PLL_OUTPUT_COUNTER Info (175013): The PLL output counter is constrained to the region (0, 18) to (0, 63) due to related logic Info (175021): The PLL output counter was placed in location PLLOUTPUTCOUNTER_X0_Y21_N1 Error (175022): The global or regional clock driver could not be placed in any location to satisfy its connectivity requirements Info (175029): 30 locations affected Info (175029): CLKCTRL_G0 Info (175029): CLKCTRL_G1 Info (175029): CLKCTRL_G2 Info (175029): CLKCTRL_G3 Info (175029): CLKCTRL_R82 Info (175029): CLKCTRL_R83 Info (175029): CLKCTRL_R84 Info (175029): CLKCTRL_R85 Info (175029): CLKCTRL_R86 Info (175029): CLKCTRL_R87 Info (175029): CLKCTRL_R58 Info (175029): CLKCTRL_R59 Info (175029): and 18 more locations not displayed

[Altera_Forum]

I am going to go out on a limb, based on issues with clock control blocks and a CLKENBL signal, and guess that there is a resource usage limitation in your device, presumably a Cyclone V, related to routing for clock control blocks. Perhaps the next step is to look at the resource consumption report in the compilation output specifically at the PLL and clock control block usage. Perhaps you need to try to combine PLLs or use a PLL on the same side of the device as the transceiver?

[Altera_Forum]

Thanks for your reply. 

 Yes, the SoCKit has a Cyclone V on it. Maybe it is because I am very new to Quartus: What do you mean by "use a PLL on the same side of the device as the transceiver"? Is there a way to use a certain PLL? It says that I am using 1/15 PLLs, so this is not a limitation of PLLs but maybe a limitation of paths? I can not find a value about clock control blocks.  Well, I need to say that I maybe miss a important part and why the title says "with external FIFO": If I use the internal FIFO, it works with a PLL. In the near future I want to use multiport TSE that is why I am not using internal FIFO anymore.  To summarize:  internal FIFO: hsmc_ref_clk => pcs_ref_clk OK (but wrong frequency) hsmc_ref_clk => PLL => pcs_ref_clk OK external FIFO: hsmc_ref_clk => pcs_ref_clk OK (but wrong frequency) hsmc_ref_clk => PLL => pcs_ref_clk Error seen in the first post   The only combination which is not working is the one I need :D

[Altera_Forum]

I'm guessing that internally the TSE, when interfaced with transceivers, does something different with the global and or regional clock assignments depending on whether its an internal or external FIFO. You can look at this in the generated code for the TSE. 

 If you instantiate the PLL at the top level with the mega-wizard (i.e. outside of QSYS) then you should see options for specific location assignments auto/top/bottom/left/right for the PLL, or in any case I seem to recall seeing such options for the cyclone III.  You might also have a look at the Altera document related to PLLs and global clock routing resources in the Cyclone V.

[Altera_Forum]

I don't want to hijack this thread if the issue has not been resolved, but I am also trying to utilize the HSMC_REF_CLK (at 100MHz) for the same exact task (to feed the TSE). My issue, however, is that I am not even getting a clock signal from the HSMC_REF_CLK (I'm using Pin 9 as an input into my design which, according to the schematic, is the HSMC_REF_CLK). For the OP or anyone else who can answer, did you have to do any set-up with the 5338 to get this signal to work? Or are you just using it as you would any other clock signal (e.g., the 50 MHz clock, which works just fine)?  

 Note: I have never used a diff pair clock signal before, so perhaps my design is flawed?  Thank you!

[Altera_Forum]

No, I made no set up for the SI5338Q. The default (on SoCKit) is that all four clocks are enabled. 

 Pin P9 is right and I/O standard is HCSL.  However, I still try to find out if there is a PLL on the board to solve my problem

[Altera_Forum]

I'm trying to accomplish the same task, so if I find an answer I will post it... let me know if you solve your problem in the meantime. (Of course, I need to get the clock to work first... I have the exact settings that you state, with no output!)

[Altera_Forum]

The funny thing for me is that I can get my design to compile with a PLL (100MHz input, 125MHz output) with the PLL outclock connected to the TSE ref_clk -- no errors. For me, I have no signal from the HSMC_REF_CLK (100MHz) that should be utilizing Pin 9 (with HCSL I/O Standard). I've tried two Dev Kits, same thing. I even ask a fellow EE next door to try to test the 100MHz clock signal -- he too cannot get a signal from this clock. Not that it will solve your issue, but will you verify (with a blink program or using signal tap) that you are getting a signal on Pin 9? 

 Back to your issue, I haven't been able to test any of the theories that are in my head, but one thought that comes to mind... have you tried a clock control block (ALTCLKCTRL) prior to your PLL?   References:  http://www.altera.com/support/kdb/solutions/rd03302012_430.html http://www.altera.com/support/kdb/solutions/rd09252012_453.html http://www.altera.com/literature/ug/ug_altclock.pdf

[Altera_Forum]

I tried a ALTCLKTCTRL and also different PLLs still with no progress. 

 Does anyone have an idea what I exactly need to do? Seems to be a dead end for me until someone really knows how to solve this issue.

[Altera_Forum]

I was in contact with Terasic and I solved the problem by reconfiguring the SI5338Q. I set the hsmc_ref_clk to 125MHz, so there is no need anymore for a PLL.