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TSE memory usage

Altera_Forum
Honored Contributor I
1,068 Views

Happy new year, everybody! 

 

when I check resource usage in my design, I get the following readout: 

 

http://i51.tinypic.com/dm7cc2.gif  

 

Do I understand correctly, this means the TSE is wasting M9K-Blocks for as few as 2 bits of data? 

As I am already low on M9Ks, is there something I can do about it?
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3 Replies
Altera_Forum
Honored Contributor I
70 Views

Look at it in the fitter report, rather than the synthesis, just to be sure.  

If it really is wasting a memory block, look at Assignments -> Settings -> Analysis & Synthesis -> More Settings. There are three settings called "Allow any Sizer for RAM/ROM/Shift Register". These should default to off, but if turned on will allow tiny memories to go into memory blocks.
Altera_Forum
Honored Contributor I
70 Views

Additionally I found these settings to influence behaviour: 

- Auto RAM replacement was ON 

- Auto RAM to Logic Cell Conversion was OFF 

(just to be complete) 

 

Thanks, that's what I was looking for - I just gained ~20 M9K-Blocks.
Altera_Forum
Honored Contributor I
70 Views

The latter two, especially Auto RAM Replacement On, are On by default and generally a good thing, as it only tries to put larger inferred RAMs into the memory blocks. If you're worred about RAM usage, it's probably worth looking at the RAM usage before and after and comparing. Note that this is the global setting, but can be applied to differently to any sub-hierarchies. Just right click on the hierarchy in the Project Navigator, Locate -> Assignment Editor, and make the assignment there.

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