Community
cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
Honored Contributor I
720 Views

TSE problem

Hi, 

 

I have custom packet generator in QSYS feeding TSE in Cyclone IV development kit. 

 

Behaviour is strange. Some times the system works as expected, ethernet packets come out and I see them being routed to destination NIC by monitoring two lights blinkin on ethernet switch. I also can capture them by WireShark. 

 

But then suddenly, (probably after new FPGA configuration trhough embedded USB Blaster) the only light that blinks on the switch is FPGA port. The destination NIC port does not blink (and no activity on WireShark). 

 

This might last for hours, and then suddenly everything starts working again. 

 

I have tracked it not to be due my design (same design has been working and not working). 

 

I have also instantiated ocp_timeout_indicator to see if Open Core timeout problem is hitting me, bu no indication to that is seen. 

 

Looking the input port of TSE by SignalTap, everything is as expected. 

 

Also TimeQuest does not warn other than altera_reserved_tck. 

 

Any ideas what could cause this? 

 

Running Quartus 12.0SP2 on Ubuntu 10.10 (64-bit linux, 32-bit quartus I guess). 

 

-Topi
0 Kudos
1 Reply
Highlighted
Honored Contributor I
12 Views

 

--- Quote Start ---  

the only light that blinks on the switch is FPGA port. The destination NIC port does not blink (and no activity on WireShark). 

--- Quote End ---  

If the switch doesn't send the packet to the destination NIC, it means that something is probably wrong in the header of the packet it receives from the FPGA. Can you configure a switch port as a monitor, so that all the packets are sent to the destination NIC and picked up by Wireshark? Alternatively you could also directly connect your destination NIC to the FPGA board, without using a switch.
0 Kudos