FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
6536 Discussions

Testing RX SERDES with a known value

Altera_Forum
Honored Contributor II
‎11-28-2014 06:19 PM
1,589 Views

I'm testing my system and I'd like to associate a known value to a RX Serdes Input. When instantiating it in top module I'd like to put my 8ch like .rx_in(8'hFF) but when I tried to do that I just receive this error below 

 

Error (15871): Input port DATAIN of DDIO_IN primitive "SERDES:serdes|altlvds_rx:ALTLVDS_RX_component|SERDES_lvds_rx:auto_generated|SERDES_ddio_in:ddio_in|ddio_ina_1" must come from an I/O IBUF or DELAY_CHAIN primitive 

 

I tried to create a reg and the associate a reg to rx_in but again without success. 

 

Thanks 

Danilo
0 Kudos

Link Copied

1 Reply
Altera_Forum
Honored Contributor II
‎11-28-2014 08:33 PM
511 Views

if you are simulting then use testbench to instantiate your design and feed input through io

0 Kudos
Copy link
Reply

Community support is provided Monday to Friday. Other contact methods are available here.

Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.

For more complete information about compiler optimizations, see our Optimization Notice.