The DDR2 Controller with UniPHY has a port called "afi_reset". What causes this signal to assert? We are experiencing this signal asserting on a small subset of custom fpga boards. We are trying to debug the exact cause.

[SPols]

We have made a set of custom boards incorporating the Altera chip as documented in the information of the form. We have an issue directly related to the DDR2 controller on 2 of the 12 boards we have tested so far. What happens on the boards with issues is the DDR2 controller signal "afi_reset" is asserted periodically during operation. If this assertion happens at the wrong time it will create errors. We are wondering what is the cause of this "afi_reset" assertion and what can we do on our end to make sure it doesn't happen? I am guessing it has to do with PCB variability given that it only happens on a small percent of boards.

Thanks

FPGA device used is Cyclone V GT.

[NurAida_A_Intel]

Dear SPols,

Thank you for joining this Intel Community.

The afi_reset signal will assert based on 2 conditions:

1. PHY is reset
2. PLL loses lock : This indicate that your afi_clk is not stable yet thus it will assert the reset signal until the PLL is locked.

For more details, you can refer to this user guide : https://www.intel.com/content/dam/altera-www/global/ja_JP/pdfs/literature/hb/external-memory/emi_ddr3up_ug.pdf

Hope this helps

Regards,

NAli1

[SPols]

Hi NAli1,

Thank you for getting back to me. Do you know what can cause a reset to the PHY? Also do you know why the PLL might lose lock? I have two circuit boards, with the exact same hardware and Altera firmware but this issue only happens with one of them. Does anything come to mind?

Thanks

[NurAida_A_Intel]

Dear Spols,

The reset pin is introduced for system stability. This Reset pin is an active-low signal and the main cause this reset pin asserted is due to the PLL lose lock.

And the PLL might lose lock due to a number of possible causes. As far as I know, two main reasons of that kind of behavioral is clock source quality and temperature in which device is working. I would suggest going through below check-list that may help.

https://www.intel.com/content/www/us/en/programmable/support/support-resources/operation-and-testing/pll-and-clock-management/pll-loss-lock.html

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/support/devices/pll/pll-loss-of-lock-checklist.pdf

Hopefully this is helpful . 😊

Thanks

Regards,

NAli1