Regarding the use of the Seriallite II protocol in hardware: The chip we use is the EP2AGX65DF29C6N of the Arria II GX series. When using quartus II to allocate the pins, it is not clear how the input and output of the Seriallite II IP core should be connected to the chip pins.
Regarding the pin connection, the specific problem is this: On the SLII IP, there are data input and output pins, such as rxin, txout, rxrdp_dat, txrdp_dat, etc., as well as some other signal pins (with bsf attached).
And on the FPGA chip we use (with pin diagram attached), there are ten banks, of which there are two GXB banks, divided into general purpose I/O, high-speed differential I/O, high-speed differential I/O with DPA, and we also want to use LVDS.
Therefore, we want to find out which bank or IO port these signals on the SLII IP should be connected to, and whether you have any other opinions and suggestions on the use of LVDS in this process.
Hereby ask for help, hoping to solve the problem.
Thanks for your request.
Can you check if pin connection guideline doc may help?
And also you can refer to pinout list below on definition of each pin:
Thank you for your reply.
I have read the two documents you sent. They are all about FPGAs, but our problem is mainly that we want to use the Seriallite II IP core and cannot confirm the connection between the signal and the FPGA pins. We are worried that the chip will be damaged during use, So I want to ask the engineer for confirmation.
Looking forward to your reply.
If we look at section "Differential I/O Pins" on page 5,6 of https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/dp/arria-ii-gx/pcg-01007.pd...
it mentioned the pin convention for either true LVDS transmitter/receiver, then from the pin list files in this link (choose your used device):
look for the pin location that mapping the pin convention.
Let me know if you have further question.
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