The difference of ALt_pll/Altera pll

[TGao]

Dear Sir/Madam,

I'm porting projects from max10 to cyclone v, there're some difference in pll IP, as below,

1. the ​width of "phasecounterselect" are 3,but in cylone v, it's 5, difference?

2. How do I use "Phase_en" ? It's has't this pin in max10 pll.

3. Is “phase-step” equal to “scan_clk ”？

Ted.Gao

[Rahul_S_Intel1]

Hi ,

 In Max 10,, you have Alt PLl and Cyclone V have altera pll.

Both PLL have different architectures,

To answer your question.

The register mapping of two devices are different.

Phasecounterslelect only 3 bits to select m or c couters 

Refe Table :12 Max 10 user guide

In cyclone V Avalon bus is using for the reconfiguration on

For phase_en , signals are using in the Cyclone V devices not on Max 10, kindly find user guide [SR1] Table no: 6 for detailed explanation.

 >> phase-step” equal to “scan_clk

Both are different ,refer page no: 58 of this document