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5949 Discussions

Timing Constraints for Cyclone 10GX PHY Interlaken

MHahn4
New Contributor I
617 Views

Hi,

 

I'm trying to run the PHY transceivers on a Cyclone 10GX in Interlaken mode.

 

While synthesising, there appears a "Timing requirements not met" critical warning. The problematic paths are for the following clocks:

 

unitname|xcvr_native_a10_0|rx_coreclkin

unitname|xcvr_native_a10_0|rx_pma_clk

unitname|xcvr_native_a10_0|tx_coreclkin

unitname|xcvr_native_a10_0|tx_pma_clk

 

I suppose there are some timing constraints missing? The only information about the timing constraints I could found, is to add

derive_pll_clocks -create_base_clocks

to the sdc file. But this doesn't solve the problem but adds another warning:

 

"Warning(332157): The base clock assignment for generated clock unitname|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|gen_twentynm_hssi_tx_pld_pcs_interface.inst_twentynm_hssi_tx_pld_pcs_interface|pld_tx_clk cannot be derived"

 

Can you please give me a hint, how the required timing constraints have to look like?

 

Thanks

0 Kudos
6 Replies
HBhat2
New Contributor II
316 Views

Hi,

 

Along with derive_pll_clocks, I think to mention create_clock constraint for input reference clock(s) as well.

 

create_clock -name {pll_refclk0} -period 10 [get_ports {pll_refclk0}]

here, pll_refclk0 is the input clock port in the top module and 10 is 10ns (ie 100MHz input clock).

 

With Regards,

HPB

MHahn4
New Contributor I
316 Views

I did that already and the two input clocks are detected wth the correct frequency during synthesis.

 

That's my full sdc-file:

create_clock -name {CLK_100MHz} -period 10.000 -waveform { 0.000 5.000 } [get_ports {CLK_100MHz}] derive_pll_clocks   create_clock -name {~ALTERA_CLKUSR~} -period 10.000 -waveform { 0.000 5.000 } { ~ALTERA_CLKUSR~~ibuf|o }

 

Nathan_R_Intel
Employee
316 Views

Do you still observe any other warnings. Basically, you only need to create clocks for the reference clock and pll clocks and it should be sufficient.

 

Regards,

Nathan

MHahn4
New Contributor I
316 Views

Yes. I've even tried a minimal design with loop back on the parallel data and only the three IP Cores (PHY, ATX-PLL, ResetController), but the timing errors still exist.

Nathan_R_Intel
Employee
316 Views

Hie,

 

In that case, could you send you attach your design achieve (.qar) for me to check what is causing the timing error. Also, do advice which Quartus version being used.

 

 

Regards,

Nathan

Nathan_R_Intel
Employee
316 Views

Hie,

 

Could you send me your simplified design achieve (.qar) for me to check what is causing the timing error. Also do advice which quartus version being used.

 

Regards,

Nathan

 

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